The channel routing problem in VLSI design is to route a specified interconnection among modules in as small an area as possible. Hashimoto and Stevens (1971) proposed an algorithm for solving the two-layer channel routing problem in the absence of vertical constraints. In this paper, we analyze this algorithm in two different ways. In the first analysis, we show that a graph-theoretic realization, algorithm MCC1, runs in O(m + n + e) time, where m is the size of the channel specification of n nets, and e is the size of the complement of the horizontal constraint graph. In the second analysis, algorithm MCC2, we show that a time complexity of O(m + n log n) can be achieved. Algorithms MCC1 and MCC2 guarantee optimum routing solutions under the multi-layer V/sub i+1/H/sub i/ (i/spl ges/1) routing model, where the horizontal and vertical layers of interconnect alternate. Finally, we consider the problem of minimizing the total net wire length in the V/sub i+1/H/sub i/ (i/spl ges/1) routing model. Given a channel specification and a partition of the set of nets (where the nets within each part of the partition are non-overlapping), we propose an O(m + d/sub max/log d/sub max/) time algorithm for minimizing the total net wire length, subject to the condition that nets from a part of the partition are assigned to the same track. All our solutions use the minimum number of via holes. >

https://ieeexplore.ieee.org/iel2/1063/7689/00320053.pdf

Resolving horizontal constraints and minimizing net wire length for multi-layer channel routing

An image-based LCD positioning system utilizing the modified FHT method

Run-time synchronization overhead is a crucial factor in limiting speedup for parallel computers. In this paper, we present a new two-phase algorithm for removing redundant dependencies and minimizing interprocessor synchronizations when scheduling an acyclic task graph onto a multiprocessor system. The first phase removes redundant dependencies before scheduling; the second phase eliminates interprocessor synchronizations after scheduling. In a simulation using randomly generated task graphs, on the average, 98.28% of the dependencies are eliminated in the first phase, and 65.86% of the remaining dependencies are eliminated during the second phase, for a total of 99.41% removed. The approach has also been applied to some benchmark task graphs. The two-phase algorithm, which hasO(n3) time complexity andO(n2) space complexity, utilizes a new algorithm which computes the transitive closure and reduction at the same time, storing results in a single matrix.

Minimizing redundant dependencies and interprocessor synchronizations

An optimal channel routing algorithm for a detailed two-layer channel routing is proposed. Through the inclusion of appropriate net characteristic information in the node searching function, this algorithm expands far fewer nodes than Wang's (1990) algorithm to obtain optimum solutions on all of the benchmark problems presented by T. Yoshimura and E.S. Kuh (1982). Since the two-layer model has a minimum number of vias and a minimum length of wires, the proposed algorithm is suitable for the routing of channels with mixed analog/digital signals. >

An efficient optimum channel routing algorithm

The computation model on which the algorithms are developed is the reconfigurable array of processors with wider bus networks (abbreviated to RAPWBN). The main difference between the RAPWBN model and other existing reconfigurable parallel processing systems is that the bus width of each network is bounded within the range [2,[/spl radic/(N)]]. Such a strategy not only saves the silicon area of the chip as well as increases the computational power enormously, but the strategy also allows the execution speed of the proposed algorithms to be tuned by the bus bandwidth. To demonstrate the computational power of the RAPWBN, the channel-assignment problem is derived in this paper. For the channel-assignment problem with N pairs of components, we first design an O(T + [N//spl omega/]) time parallel algorithm using 2N processors with a 2N-row by 2N-column bus network, where the bus width of each bus network is /spl omega/-bit for 2 /spl les/ /spl omega/ /spl les/ [/spl radic/N] and T = [log/sub /spl omega//N] + 1. By tuning the bus bandwidth to the natural log N-bit and the extended N/sup 1/c/-bit (N/sup 1/c/ > log N) for any constant c and c /spl ges/ 1, two more results which run in O(log N/log log N) and O(1) time, respectively, are also derived. When compared to the algorithms proposed by Olariu et al. [17] and Lin [14], it is shown that our algorithm runs in the equivalent time complexity while significantly reducing the number of processors to O(N).

Optimal algorithms for the channel-assignment problem on a reconfigurable array of processors with wider bus networks

An algorithm known as optimal channel routing (OCR) is proposed which finds an optimal solution for the channel routing problem in VLSI design. The algorithm is an A* algorithm with good heuristics and dominance rules for terminating unnecessary nodes in the searching tree. Experimental results, agreeing with theoretical analysis, show that it behaves quite well in average cases. An optimal solution is obtained for the Deutsch difficult case in 5.5-min-CPU time after the algorithm is implemented in Pascal and run on a VAX 11/750 computer. >

J.-S. Wang

Papers

An efficient channel routing algorithm to yield an optimal solution