A hardware design of a configurable and extensible processor named Tcore, which is based on transport triggered architecture (TTA)? is presented in this paper.  Due to its flexibility, the Tcore can be used as an application specific processor, especially as a coprocessor for different DSP applications. We have configured Tcore to an instruction level parallel processor to support the application of MP3 IMDCT in a SoC and have been fully verified on FPGA. The results show the advantage of using this configurable processor in terms of performance in computation, flexibility in application, limited effort in design and reduction on silicon area.

Design of a Configurable and Extensible Tcore Processor Based on Transport Triggered Architecture

A parallel architecture for efficient hardware implementation of Rivest Shamir Adleman (RSA) cryptography is proposed. Residue number system (RNS) is introduced to realize high parallelism, thus all the elements under the same base are independent of each other and can be computed in parallel. Moreover, a simple and fast base transformation is used to achieve RNS Montgomery modular multiplication algorithm, which facilitates hardware implementation. Based on transport triggered architecture (TTA), the proposed architecture is designed to evaluate the performance and feasibility of the algorithm. With these optimizations, a decryption rate of 106 kbps can be achieved for 1 024-b RSA at the frequency of 100 MHz.

Hardware architecture for RSA cryptography based on residue number system

Optimization of a novel programmable data-flow crypto processor using NSGA-II algorithm.

....................................................................................................................I PREFACE.....................................................................................................................III CONTENTS................................................................................................................... V LIST OF PUBLICATIONS....................................................................................... VII SUPPLEMENTARY PUBLICATIONS...............................................................................VIII LIST OF ABBREVIATIONS......................................................................................XI

Design of Quality of Service Support for Wireless Local Area Networks

In this chapter we discuss the challenges for future communication systems, stemming from changing network security environments and the emergence of Internet of Things and sensor networks, all combined with increasing security and privacy requirements. We provide an initial step towards solving these challenges by presenting a design methodology and flow for Software Defined Secure Communications platform, based on our previous TACO platform. With foundations in Transport Triggered Architecture protocol processing applications, the TACO platform is modified by including support to security in the design. We discuss cryptography fundamentals, cryptographic primitives, and adaptive cryptography concepts, and present approaches for their inclusion in the SDSC platform. We discuss briefly a case study of RSA implemented on our platform, and the limited but encouraging results that this study provided. Finally we discuss potential target applications that could benefit from the SDSC platform and design methodology.

Towards Adaptive Cryptography and Security with Software Defined Platforms

The paper studies a configurable processor architecture, transport triggered architecture (TTA), for encryption algorithm implementations. The automatic TTA design space exploration is applied and configurations with good cost-performance ratio are found. It is shown that TTAs are at least equal to commercial processors in performance. According to earlier studies the performance level is also achieved at far lower cost. This encourages further development with tuned functionality.

J. Saarvinen

Papers

Implementation of encryption algorithms on transport triggered architectures