Describes a reconfigurable computer engine called the Data-Flow Functional Computer (DFFC), which is dedicated to rapid prototyping of real-time vision automata. The computer consists of a regular 3D array of very coarse grain application-specific FPGAs, called the 'field-programmable operator array' (FPOA). Each FPOA includes two configurable data paths and ten input/output ports. Specific development tools allow easy and efficient use of the computer. A high-level description (in a functional language) is compiled into a DFFC configuration using an operator library. Several significant applications (connected component labelling, nonlinear filtering, coloured object tracking) have been implemented using our tools. An environment for automatic derivation of vision automata from a DFFC configuration is currently under development. >

A reconfigurable compute engine for real-time vision automata prototyping

Les travaux presentes dans ce memoire s'inscrivent dans la problematique dite d'adequation algorithme architecture. Ils concernent la conception et le developpement d'outils logiciels permettant de faire du prototypage rapide d'applications paralleles de vision artificielle sur des architectures de type MIMD a memoire distribuee. De tels outils ont pour objectif de faciliter l'evaluation rapide d'un ensemble de solutions vis a vis d'un probleme donne en diminuant de maniere drastique les temps de cycle conception-implantation-validation des applications. L'outil SKiPPER developpe dans le cadre de ces travaux est base sur le concept des squelettes de parallelisation. Ceux-ci representent des constructeurs generiques de haut niveau encapsulant des formes communes de parallelisme tout en dissimulant les details relatifs a l'exploitation de ce parallelisme sur la plate-forme cible. Au niveau langage, la specification des squelettes est realisee au sein du langage fonctionnel Caml sous la forme de fonctions d'ordre superieur. Ainsi, la specification d'une application est un programme purement fonctionnel dans lequel l'expression du parallelisme est limitee au choix et a l'instanciation des squelettes choisis dans une base pre-definie. L'environnement de developpement SKiPPER est organise autour de trois modules realisant respectivement l'expansion du code fonctionnel en un graphe flot de donnees (outil Dromadaire), le placement-ordonnancement de ce graphe sur l'architecture materielle (outil SynDEx developpe a l'INRIA) et la generation de code cible final pour l'architecture cible (la machine Transvision du LASMEA dans notre cas). L'applicabilite des concepts mis en \oe uvre dans SKiPPER et des outils developpes conjointement est demontree egalement dans les travaux presentes dans ce memoire. Diverses applications de complexite realiste (etiquetage en composantes connexes, detection et suivi de signalisation horizontale autoroutiere) ont ete parallelisees automatiquement par l'environnement SKiPPER validant ainsi l'objectif initial de prototypage rapide d'applications paralleles de vision artificielle a fortes contraintes temporelles sur architecture dediee.

https://tel.archives-ouvertes.fr/tel-00550828/document

Prototypage rapide d'applications parallèles de vision artificielle par squelettes fonctionnels

We present AVSynDEx (concatenation of AVS + SynDEx), a rapid prototyping process aiming to the implementation of digital signal processing applications on mixed architectures (multi-DSP + FPGA). This process is based on the use of widely available and efficient CAD tools established along the design process so that most of the implementation tasks become automatic. These tools and architectures are judiciously selected and integrated during the implementation process to help a signal processing specialist without relevant hardware experience. We have automated the translation between the different levels of the process to increase and secure it. One main advantage is that only a signal processing designer is needed, all the other specialized manual tasks being transparent in this prototyping methodology, hereby reducing the implementation time.

/pdf/avsyndex-a-rapid-prototyping-process-dedicated-to-the-3d3yt2gno5.pdf

AVSynDEx: a rapid prototyping process dedicated to the implementation of digital image processing applications on multi-DSP and FPGA architectures

This work proposes and implements a reconfigurable parallel architecture based on dataflow for numerical computation, named PRADA. This architecture uses concepts of parallel processing to obtain a scalable performance and the dataflow concept for controlling the parallel execution of instructions. PRADA is composed by a control unit and several processing elements (PEs). In the control unit, there are several functional blocks, including data and instruction memories. Each PE is composed by an ALU and buffers. PRADA is organised as a cluster, in which several independent dataflow modules are interconnected together. PRADA was developed in VHDL and implemented in reconfigurable hardware using a FPGA device. Therefore, it can offer high performance, scalability and customised solutions for engineering problems. Results of the application of PRADA to the computation of a digital filter and a cryptography algorithm are presented. Results are also compared with other different architectures, such as microprocessors, ASICs, DSPs, reconfigurable architectures and dataflow architectures. In most cases, PRADA achieved either competitive or higher performance than the other architectures, regarding the measures used. Overall results suggest that this architecture can be applied to several classes of problems that may require a high throughput, such as cryptography, optimisation and scientific computing.

PRADA: a high-performance reconfigurable parallel architecture based on the dataflow model

Universit ´ e blaise pascal - clermont ii

The authors present three examples of real-time image processing applications that were implemented on a data-flow architecture developed at the ETCA. Low-level image processing is performed on a regular three-dimensional network of 1024 custom data-flow processors. Image features previously extracted in the low-level step are handled by a two-dimensional network of 12 general purpose processors. Fast prototyping of real-time image processing applications is achieved through a programming environment including a complete stream from functional programming specification to network configuration. A large class of algorithms can be implemented. Among them the authors describe a nonlinear filter, a connected component labeling and a colored object tracking.

Implementing image processing applications on a real-time architecture

The authors present a wavefront array processor architecture developed at ETCA and dedicated to real-time processing of digital video streams. The core of the architecture is a mesh-connected three-dimensional network of 1024 custom processing elements. Each processing element can perform up to 50 millions 8- or 16-bit operations per second, working with a 25 MHz clock frequency. Thus algorithms are facilitated by the routing capabilities of each processing element. The machine is fully data-driven and is a "pure" data-flow one since there are no address flows. Algorithms and architecture are described using a data-flow graphs formalism. Image processing applications are decomposed into elementary operators that correspond to physical processors in a one to one fashion. Several algorithms can be simultaneously mapped and independently executed on the processor network. Referring to the academic wavefront array paradigm, "exotic features" are exhibited. They are related to the wavefront propagation mode at run-time and to the heterogeneous nature of data-flow that are piped into or from the processor network. These features are shown to make the architecture well-suited for fast prototyping of low-level image processing automata. >

J. Serot

Papers

Implementing image processing applications on a real-time architecture

A wavefront array processor for on the fly processing of digital video streams