Neural nets using capacitive structures are adapted for construction in complementary metal-oxide-semiconductor integrated-circuit technology. In each neural net layer synapse input signals are applied to the inverting and non-inverting input terminals of each of a plurality of differential-input non-linear amplifiers by a respective pair of capacitors, which non-linear amplifiers generate respective axon responses. In certain of these neural nets, arrangements are described that make the capacitive structures bilaterally responsive, so that back-propagation calculations can be performed to alter the relative values of capacitors in each pair thereof, which is done during training of certain of the neural nets described.

Neural net using capacitive structures connecting input lines and differentially sensed output line pairs

An Analog Decision Network Abstract A circuit for realizing controllable analog weights as used, for example, in template matching circuits. Analog weights are obtained by storing charge on two primary capacitors and by controlling the potential difference between the two primary capacitors. The control of charge on the two capacitors is effected with a bridging connection between the two primary capacitors. In one embodiment, the bridging connection contains two switches and an MOS transistor.

Analog decision network

An array of weighted summation circuits, N in number, each generate a weighted sum response to the same plurality of input signals, M in number. Each weighted summation circuit includes at least one corresponding capacitive element for determining the weighting of each of the input signals within that weighted summation circuit. At least one corresponding capacitive element is of a programmable type having its capacitance value determined in accordance with the bits of a digital word received at a control word port thereof. The array of weighted summation circuits are preferably constructed in integrated circuit form together with an interstitial memory having respective word storage elements for temporarily storing the digital words applied to the control word ports of nearby capacitive elements in the integrated circuitry.

Weighted summation circuitry with digitally controlled capacitive structures

Publisher Summary This chapter presents the design, fabrication, and performance of the charged couple device (CCD) images. Decrease in transfer inefficiency over the surface-channel CCD technology is generally accepted to be at least an order of magnitude. Because of the fact that these commercially available devices are primarily line-scan image sensors and two-dimensional arrays with intrinsic silicon spectral response, it is intentional that there will be a heavy emphasis on these types of devices. The modulation-transfer function describes the fidelity of an imaging system by giving the attenuation of an image signal as a function of spatial frequency. In CCD image sensors, the MTF is the result of several parameters: the photo element aperture, the optical cross talk, the charge-transfer inefficiency, and the preamplifier characteristics. An n -channel CCD line-scan image sensor can be fabricated much like a high-density NMOS memory device. They both use two levels of polysilicon gates. Ion implantation is essential as a means of doping and is used at least twice in the course of making a typical two-phase device: once to form the n -channel and again to form the barriers that are located under the gaps in the first level of poly-Si along the CCD registers. A CCD signal-processing device that could appropriately be used in a camera for image processing is considered for application in spacecraft navigation and camera pointing. A significant feature of this technology is the high uniformity of response that is possible in the case of illumination from the silicon side.

Design, Fabrication, and Performance of CCD Imagers

This invention concerns an analog-to-digital correlator with programmable coefficients with values of +1, -1 or 0. This correlator comprises a charge-transfer shift register to receive samples of the analog input signal for correlation, and two programmable digital-output shift registers, followed by memories to establish coefficients with values of +1, -1 or 0. Depending on the signal available at the digital register outputs: reading of charges is blocked on the analog register, corresponding to establishment of coefficient 0; reading of charges occurs, reaching either the positive or the negative input of a differential amplifier, corresponding to the establishment of coefficient +1 or -1.

Analog-to-digital correlator with programmable coefficients with values of +1, -1 or 0

This paper describes the operational features and performance of a fully-integrated programmable transversal filter (p.t.f.), using c.c.d./m.o.s.t. technology. The choice of filter architecture for a prototype realization is discussed with particular reference to a novel multiplier array implementation using a single, time-multiplexed m.o.s. transistor. The performance characteristics of a prototype, 64-point filter design based on this approach are detailed with reference to frequency- and matched- filtering. Techniques for optimizing the performance of this analogue filter structure under microprocessor control are suggested, through the iterative adaption of the filter impulse response, and equivalent results are given to show the improvement gained. An alternative technique for improving the filter characteristics which enables it to optimize the processing of signals under certain conditions has also been demonstrated. This adaptive filter configuration is based on the linear Widrow least-mean-square (W.l.m.s.) algorithm, and has been realized using the p.t.f. with minimal additional circuitry, without the requirement for a microprocessor.A general signal-processing module of 256-points using four cascaded filters is described; and results are presented when it is used in a sonar, matched-filtering experiment. Also a 64-point adaptive filter based on a prototype p.t.f. is described and its application to inverse filtering and self-tuning filtering is demonstrated.Finally, the potential of this miniature integrated filter for sonar-type applications is reviewed against new developments. In particular, a 256-point monolithic p.t.f.currently in development, and the concept of a dedicated adaptive filter in single chip form.

J.W. Arthur

Papers

A monolithic c.c.d. programmable transversal filter for analogue signal processing