The realization of a digital recording system using partial-response class-IV signaling with maximum-likelihood sequence detection (MLSD) is described. To perform MLSD at the high data rates encountered in recording systems, a simple implementation of the Viterbi detector based on a difference-metric algorithm is developed. Decision-directed schemes for gain control and timing recovery, for tracking variations of the gain and timing phase during data readback, and for fast initial adjustment from a known preamble are presented. The dynamic behavior of the control algorithms was studied by computer simulations. Coding was used to facilitate timing recovery and gain control, to limit the path memory length of the Viterbi detector, and to allow fast and reliable startup of the receiver. The design and properties of rate 8/9 constrained codes are examined. The problem of equalization is addressed, and analog and combined analog/digital filter implementations are developed. A simple adaptive equalizer capable of compensating variations of the recording channel characteristics with track radius and/or head-to-medium distance is described. >

A PRML system for digital magnetic recording

A class IV partial response, maximum likelihood data channel for a disk drive includes an encoder connected to a data sequencer for converting user data blocks into a predetermined 8/9ths code such as a (0,4,4,) code. A precoder converts the 8/9ths code into class IV code. An analog write driver supplies the class IV code to a data transducer head during data write-to-disk operations. A read channel connected to the head amplifies and conditions analog signals during data read operations. A quantizer produces samples of the analog signals in accordance with a quantization clock generated by a clock generator. An adaptive FIR filter means is conditions the data samples in accordance with selectable, adaptive filter coefficients. A Viterbi detector puts out the class IV code from the filtered and quantized samples. A postcoder converts the detected class IV code into detected 8/9ths code. A decoder converts the detected 8/9ths code into user data and supplies user data to the sequencer. The programmable FIR filter is provided with servo coefficients during reading of the servo sectors, and an asynchronous servo detector detects head position information from the quantized and filtered samples without phase locking of the quantization clock generator to the quantized servo samples. The asynchronous servo detector is also used to aid detection of sync field preamble information before the FIR filter is fully adapted. Multi-mode gain and timing loops are also a part of the present invention.

Disk drive using PRML class IV sampling data detection with digital adaptive equalization

A class IV partial response, maximum likelihood data channel for a disk drive includes an encoder connected to a data sequencer for converting user data blocks into a predetermined 8/9ths code such as a (0,4,4,) code. A precoder conveys the 8/9ths code into class IV code. An analog write driver supplies the class IV code to a data transducer head during data write-to-disk operations. A read channel connected to the head amplifies and conditions analog signals during data read operations. A quantizer produces samples of the analog signals in accordance with a quantization clock generated by a clock generator. An adaptive FIR filter means is conditions the data samples in accordance with selectable, adaptive filter coefficients. A Viterbi detector puts out the class IV code from the filtered and quantized samples. A postcoder conveys the detected class IV code into detected 8/9ths code. A decoder converts the detected 8/9ths code into user data and supplies user data to the sequencer. The programmable FIR filter is provided with servo coefficients during reading of the servo sectors, and an asynchronous servo detector detects head position information from the quantized and filtered samples without phase locking of the quantization clock generator to the quantized servo samples. The asynchronous servo detector is also used to aid detection of sync field preamble information before the FIR filter is fully adapted. Multi-mode gain and timing loops are also a part of the present invention.

Disk drive method using zoned data recording and PRML sampling data detection with digital adaptive equalization

Describes the channel architecture, IC technology, and integration solutions used in implementing the IBM 0681 disk drive data channel. A brief description of the 0681 disk drive is given along with a block representation of the data channel. Particular focus is placed on the major channel functions: equalization, data coding and detection, gain and timing recovery, and write circuitry. Both the analog and adaptive digital equalizer sections used in the channel are described. The 0681 channel uses an IBM mixed-mode IC technology to implement all channel functions. This IC process is illustrated, along with the partial-response maximum-likelihood (PRML) chip layout. Attention is also given to the hybrid nature of the PRML channel; many channel functions are implemented using a combination of both analog and digital circuits. >

Implementation of PRML in a rigid disk drive

The performance of magnetic recording systems that include conventional modulation codes combined with multiple parity bits is studied. Various performance measures, including bit error rate at the output of time inverse precoder, byte error probability at the input of the Reed-Solomon (RS) decoder and sector error rate, are used to evaluate the performance of various coding/detection schemes. Suboptimum detection/decoding schemes consisting of a 16-state noise-predictive maximum-likelihood (NPML) detector followed by parity-based noise-predictive post-processing, and maximum-likelihood sequence detection/decoding on the combined channel/parity trellis are considered. For conventional modulation codes, it is shown that although the dual-parity post-processor gains 0.5 dB over the single-parity post-processor in terms of bit- and byte-error-rate performance, the sector-error-rate performance of both schemes is almost the same. Furthermore, the sector-error-rate performance of optimum 64-state combined channel/parity detection for the dual-parity code is shown to be approximately 0.1 dB better than that of optimum 32-state combined channel/parity detection for the single-parity code. These performance gains can be even more substantial if appropriate coding techniques that eliminate certain error events and minimize error burst length or multiparity codes in conjunction with combined parity/channel detection are used.

J.W. Rae

Papers

Implementation of PRML in a rigid disk drive

Integrating a partial response maximum likelihood data channel into the ibm 0681 disk drive