The yield of low voltage digital circuits is found to he sensitive to local gate delay variations due to uncorrelated intra-die parameter deviations. Caused by statistical deviations of the doping concentration they lead to more pronounced delay variations for minimum transistor sizes. Their influence on path delays in digital circuits is verified using a carry select adder test circuit fabricated in 0.5 and 0.35 /spl mu/m complementary metal-oxide-semiconductor (CMOS) technologies with two different threshold voltages. The increase of the path delay variations for smaller device dimensions and reduced supply voltages as well as the dependence on the path length is shown. It is found that circuits with a large number of critical paths and with a low logic depth are most sensitive to uncorrelated gate delay variations. Scenarios for future technologies show the increased impact of uncorrelated delay variations on digital design. A reduction of the maximal clock frequency of 10% is found for, for example, highly pipelined systems realized in a 0.18-/spl mu/m CMOS technology.

The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits

I DDQ Testing is a well accepted testing approach based on the observation of the quiescent current consumption. Its growing industrial implementation is based on the possibility of detecting defects which escape other more traditional testing methods. However, its application costs are higher and its effectiveness in deep submicron technologies may decrease if the current trend of leakage increase is not stopped by creative innovation.

http://ieeexplore.ieee.org/iel5/96/15737/00730416.pdf

Possibilities and limitations of IDDQ testing in submicron CMOS

The effectiveness of I/sub DDQ/ testing requires appropriate discriminability of defective and non-defective quiescent currents. Consequently, the interest in characterizing these currents is growing. In this paper we focus our attention on the non-defective I/sub DDQ/ current characterization. The dependence of I/sub DDQ/ on the channel length spread in scaled down devices is examined. The I/sub DDQ/ distribution of a subthreshold current dominant technology is obtained. Finally, I/sub DDQ/ test limits depending on acceptable yield loss and standard deviation of the channel length are determined.

I/sub DDQ/ characterization in submicron CMOS

The yield of low voltage digital circuits is found to be sensitive to local gate delay variations due to uncorrelated intra-die parameter deviations. Caused by statistical deviations of the doping concentration they lead to more pronounced delay variations for minimum transistor sizes. Their influence on path delays in digital circuits is verified using a carry select adder test circuit fabricated in 0.5 /spl mu/m CMOS technologies with two different threshold voltages. The increase of the path delay variations for smaller device dimensions and reduced supply voltages as well as the dependence on the path length is shown. It is found that for circuits with a large number of critical paths with a low logic depth are most sensitive to uncorrelated gate delay variations. Scenarios for future technologies show the increased impact of uncorrelated delay variations on digital design. A reduction of the maximal clock frequency of 9% is found for highly pipelined systems realized in a 0.18 /spl mu/m CMOS technology.

This paper proposes new current mirror layout strategies to reduce the matching sensitivity to the linear parameter gradients Effects of threshold gradients across a mirror on the matching characteristics of current mirrors are discussed The performance of new and existing layouts are compared for threshold voltage gradients at arbitrary angles through the active area Simulation results show a significant improvement in matching characteristics of the proposed structures over what is achievable with existing layout techniques in demanding applications

/pdf/current-mirror-layout-strategies-for-enhancing-matching-24y6l0ruze.pdf

Current Mirror Layout Strategies for Enhancing Matching Performance

This paper discusses manufacturability of state-of-the-art low power technologies. We report the results on two generations of bulk CMOS technologies, triple-well CMOS and Thin Film Silicon on Insulator (TFSOI) technologies. We present technology capabilities for several values of supply voltage and address the issue of performance scaling with the supply voltage reduction. Then we focus on the statistical characterization of these technologies and discuss both interchip and intrachip variations. Finally, we present the digital and analog designer perspectives on the low power IC operation.

/pdf/manufacturability-of-low-power-cmos-technology-solutions-3pkaxtdj8h.pdf

J. Wiart

Papers

Manufacturability of low power CMOS technology solutions