A method which makes it possible to define in a patterning layer openings having a first dimension that is substantially less than the feature size that can be obtained lithographically includes applying a sacrificial layer made of a material that is different from that of the patterning layer in a predetermined layer thickness on the patterning layer. Afterward, a photoresist layer is applied on the surface of the sacrificial layer, and an opening having a second dimension is defined lithographically in the photoresist layer. Afterward, an etching angle is set in a manner dependent on the layer thickness of the sacrificial layer and also the first and second dimensions, and the sacrificial layer is etched at the etching angle set. Afterward, the patterning layer is etched, the sacrificial layer is removed and a filling material is introduced into the opening produced in the patterning layer.

Sub-lithographic structures, devices including such structures, and methods for producing the same

Light is directed along a sample path towards the sample surface and along a reference path towards a reference surface such that light reflected by the sample surface and light reflected by the reference surface interfere. Relative movement is effected between the sample surface and the reference surface along a measurement path and the light intensity resulting from interference between light reflected from the reference surface and regions of the sample surface is sensed at intervals along the measurement path to provide a number of sets of light intensity data values with each light intensity data value representing the sensed light intensity associated with a corresponding one of said regions. The sets of light intensity data are processed to determine a position along the measurement path at which a predetermined feature occurs in the light intensity data for each sensed region and to enhance image data representing the intensity data to facilitate the detection by a user of the interference fringes.

Surface profiling apparatus

A method to anisotropically etch an oxide/silicide/poly sandwich structure on a silicon wafer substrate in situ, that is, using a single parallel plate plasma reactor chamber and a single inert cathode, with a variable gap between cathode and anode. This method has an oxide etch step and a silicide/poly etch step. The fully etched sandwich structure has a vertical profile at or near 90° from horizontal, with no bowing or notching.

Anisotropic etch method

A method to anisotropically etch an oxide/silicide/poly sandwich structure on a silicon wafer substrate in-situ, that is, using a single parallel plate plasma reactor chamber and a single inert cathode This method has an oxide etch step and a silicide/poly etch step, both of which are performed as plasma etch steps The process allows a continuous etch to be applied without removing the wafer from the plasma reactor chamber The fully etched sandwich structure has a vertical profile which has a controlled slope

One chamber in-situ etch process for oxide and conductive material

An improved LOCOS device isolation method for forming a field oxide is disclosed having the advantage of controllable and uniform sidewall framing of a nutride oxidation mask. This advantage is achieved by the use of a polysilicon layer overlying a nitride mask with the polysilicon providing an etching endpoint during the anisotropic etching used for sidewall formation. In one embodiment of the invention a silicon substrate is provided having a pad oxide formed on its surface and a first polysilicon stress-relief buffer layer formed overlying the pad oxide. A first nitride layer, to be used for oxidation masking during field oxide growth, is deposited overlying the first polysilicon layer. Next, a second polysilicon, etch-resistant buffer layer is deposited overlying the first nitride layer. The first nitride layer and second polysilicon layer are patterned by conventional lithography while the first polysilicon and pad oxide layers remained unpatterned. A second nitride layer is deposited overlying the patterned second polysilicon layer and exposed regions of the first polysilicon layer. Sidewalls are formed on the edges of the patterned first nitride and second polysilicon layers by anisotropically etching the second nitride layer using the first and second polysilicon layers as etching endpoints. Finally, the field oxide is grown by conventional methods. The grown field oxide exhibits reduced bird's beak length, and the resulting field separation is not limited by optical lithography resolution.

Method for locos isolation using a framed oxidation mask and a polysilicon buffer layer

An electronic process is provided for creating a small dimensioned pattern in a semiconductor device. In one embodiment, the pattern functions to electrically separate two areas of the substrate by less than a micron. A lithographic mask which does not have to utilize dimensions as small as those being formed on the semiconductor device is used to form a predetermined pattern with at least one separation region by irradiating and developing a photoresist material. A layer of buffer material below the photoresist material reacts with a reactive ion etch to form a separation area with sloping sides comprised of polymer filaments produced from the reaction. The sloped sides of the separation region provide a separation dimension in the substrate of the semiconductor structure which is significantly smaller than a corresponding dimension required to be implemented on the lithographic mask.

Micron and submicron patterning without using a lithographic mask having submicron dimensions

The present trend in submicron critical dimension process control is toward in-line SEM systems. Recently several new optical tools have been developed for application in the submicron environment. Optical metrology offers many well publicized operational advantages and in general higher throughput than an SEM. This paper reports on the application of a new optical metrology technique based on coherence probe imaging using a Linnik interferometer with incoherent, broad band illumination. Linewidth measurement is performed on three dimensional images produced by determining the degree of mutual coherence in the reference and object planes of the interferometer. The mutual coherence function is evaluated on a pixel by pixel basis as the sample is moved in the z direction. A commonly encountered problem of coherent optical metrology arises from interference produced by the interaction of the coherent light wave with material of varying optical path length. Incoherent systems offer a higher degree of immunity to material induced phase interference but suffer from poor resolution. The use of coherence probe imaging increases the resolution while preserving the positive aspects of incoherent illumination. The ability of the coherence probe microscope to perform accurate edge detection in a submicron IC fabrication process subject to a wide degree of process variance is compared with the in-line SEM. The effect of material thin film variations have been evaluated with respect to their influence on measurement accuracy and precision. Response surface models are described which illustrate the effect of thin film material factors on coherence probe measurement accuracy and precision. These factors include relative film reflectance, thin film thickness, and feature line width. The effects of resist slope variations and proximity of measured feature to other features is also evaluated. Measurement precision has been evaluated using component variance analysis to isolate the sources of measurement error relative to a 0.3 μm process tolerance.

J. William Dockrey

Papers

Micron and submicron patterning without using a lithographic mask having submicron dimensions

The Application Of Coherence Probe Microscopy For Submicron Critical Dimension Linewidth Measurement