A method for forming a CMOS device, with improved yield, performance and reliability characteristics, has been developed. Yield improvements have been addressed by the use of a dual insulator spacer, used to reduce the risk of salicide bridging, as well as the use of pocket implantation regions, used to reduce punchthrough leakage. An ultra shallow junction extension region has been created in a peripheral channel region, reducing the resistance of this region, thus enhancing the performance of the CMOS device. In addition, ultra lightly doped source and drain regions are used to relax reliability concerns, regarding hot electron injection.

CMOS device structure with reduced risk of salicide bridging and reduced resistance via use of a ultra shallow, junction extension, ion implantation

A field effect transistor (FET) operates in the enhancement mode without requiring inversion by setting the device's threshold voltage to twice the Fermi potential of the semiconductor material. The FET, referred to as a Fermi Threshold FET or Fermi-FET, has a threshold voltage which is independent of oxide thickness, channel length, drain voltage and substrate doping, the vertical electric field in the channel becomes zero, thereby maximizing carrier mobility, and minimizing hot electron effects. A high speed device, substantially independent of device dimensions is thereby provided, which may be manufactured using relaxed groundrules, to provide low cost, high yield devices. Temperature dependence of threshold voltage may also be eliminated by providing a semiconductor gate contact which neutralizes the effect of substrate contact potential. Source and drain subdiffusion regions may be provided to simultaneously maximize the punch-through and impact ionization voltages of the devices, so that short channel devices do not require scaled-down power supply voltages. Multi gate devices may be provided. An accelerator gate, adjacent the drain, may further improve performance. The Fermi-FET criteria may be maintained, while allowing for a deep channel by providing a substrate contact for the Fermi-FET and applying a substrate bias to this contact. Substrate enhancement pocket regions adjacent the source and drain regions may be provided to produce a continuous depletion region under the source, drain and channel regions to thereby minimize punch-through effects.

Fermi threshold field effect transistor

A floating-gate memory cell with an improved doping profile. After the substrate background doping has been set to a desired level (e.g. by a high dose implant and long drive in), two implants of opposite type are used to shape the doping profile of the floating-gate transistor. A boron implant is used to provide significantly increased p-type doping underneath the channel, at depths near the midpoint of the source/drain diffusions. A shallow arsenic implant partially compensates this boron implant at the surface, to set the threshold voltage as desired. The region of substantially increased p-type doping helps to suppress the lateral parasitic bipolar transistor which can otherwise suppress programmation, and also (by providing increased doping at the drain boundary) increases hot electron generation.

Floating-gate memory cell with tailored doping profile

A nonvolatile memory having a cell comprising an N+ type source region and drain region embedded in a P- type substrate and surrounded by respective P-pockets. The drain and source P-pockets are formed in two different high-angle boron implantation steps designed to optimize implantation energy and dosage for ensuring scalability of the cell and avoiding impairment of the snap-back voltage. The resulting cell also presents a higher breakdown voltage as compared with known cells.

Nonvolatile memory cell and a method for forming the same

An MOS structure and a method for making same, including the formation of el-shaped shielding members used to form one or more lightly doped drain regions to avoid short channel and punch-through problems is disclosed which comprises forming a shielding layer of an insulating material over a gate electrode on a substrate; forming another layer of a dissimilar material over the shielding layer; anisotropically etching the layer of dissimilar material to form spacer portions adjacent the sidewalls of the gate electrode; removing the portions of the shielding layer not masked by the spacer portions, leaving one or more el-shaped shielding members; removing the spacer portions; N+ or P+ implanting the substrate at a sufficiently low energy to prevent penetration of the dopant through the el-shaped shielding member to form a highly doped source/drain region in the substrate not shielded by the el-shaped shielding member or the gate electrode; N- or P- implanting the substrate at a sufficiently high energy to penetrate through the el-shaped shielding member to form a lightly doped source/drain region in the portion of the substrate adjacent the P+ or N+ source/drain regions and separating the channel region of the substrate beneath the gate electrode from the P+ or N+ source/drain region.

Method of making a high performance MOS device having LDD regions with graded junctions

An improved short-channel field effect transistor including a standard tip implant type of source and drain each disposed in the surface of a semiconductor substrate and a gate electrode positioned upon the substrate between the source and drain and control plugs disposed in the substrate and associated with and contiguous to the source and drain for eliminating substrate punch-through currents without substantially increasing the device junction capacitance.

Short-channel field effect transistor

of EP0071335A short-channel field effect transistor including a standard tip implant type of source (12, 40, 56) and drain (14, 42, 58) each disposed in the surface of a semiconductor; a gate electrode (30, 46) positioned upon the semiconductor between the source and drain, and control plugs (24, 26, 52, 54, 62, 64) contiguous with the source and drain for eliminating substrate punch-through currents without substantially increasing the device junction capacitance.

Jacob D. Haskell

Papers

Short-channel field effect transistor

Field effect transistor