An RF switch circuit and method for switching RF signals that may be fabricated using common integrated circuit materials such as silicon, particularly using insulating substrate technologies. The RF switch includes switching and shunting transistor groupings to alternatively couple RF input signals to a common RF node, each controlled by a switching control voltage (SW) or its inverse (SW_), which are approximately symmetrical about ground. The transistor groupings each comprise one or more insulating gate FET transistors connected together in a “stacked” series channel configuration, which increases the breakdown voltage across the series connected transistors and improves RF switch compression. A fully integrated RF switch is described including control logic and a negative voltage generator with the RF switch elements. In one embodiment, the fully integrated RF switch includes an oscillator, a charge pump, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit.

Switch Circuit and Method of Switching Radio Frequency Signals

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink

A monolithic integrated circuit (IC), and method of manufacturing same, that includes all RF front end or transceiver elements for a portable communication device, including a power amplifier (PA), a matching, coupling and filtering network, and an antenna switch to couple the conditioned PA signal to an antenna. An output signal sensor senses at least a voltage amplitude of the signal switched by the antenna switch, and signals a PA control circuit to limit PA output power in response to excessive values of sensed output. Stacks of multiple FETs in series to operate as a switching device may be used for implementation of the RF front end, and the method and apparatus of such stacks are claimed as subcombinations. An iClass PA architecture is described that dissipatively terminates unwanted harmonics of the PA output signal. A preferred embodiment of the RF transceiver IC includes two distinct PA circuits, two distinct receive signal amplifier circuits, and a four-way antenna switch to selectably couple a single antenna connection to any one of the four circuits.

Integrated RF front end with stacked transistor switch

A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the first and second determinations, and the circuit is operated using techniques for accumulated charge control operatively coupled to the SOI MOSFET. In one embodiment, the accumulated charge control techniques include using an accumulated charge sink operatively coupled to the SOI MOSFET body.

Method and Apparatus Improving Gate Oxide Reliability by Controlling Accumulated Charge

A method for operating a charge pump, the method including biasing a bulk of a charge pump stage so as to reduce body effect without forward biasing diodes of the charge pump stage.

Charge pump stage with body effect minimization

A negative charge pump circuit comprises a plurality of charge pump stages connected in series to each other. Each stage has a stage input terminal and a stage output terminal. A first stage has the stage input terminal connected to a reference voltage, a final stage has the stage output terminal operatively connected to an output terminal of the charge pump at which a negative voltage is developed; intermediate stages have the respective stage input terminal connected to the stage output terminal of a preceding stage and the respective stage output terminal connected to the stage input terminal of a following stage. Each stage comprises a first N-channel MOSFET with a first electrode connected to the stage input terminal and a second electrode connected to the stage output terminal, a second N-channel MOSFET with a first electrode connected to the stage output terminal and a second electrode connected to a gate electrode of the first N-channel MOSFET, a boost capacitor with one terminal connected to the gate electrode of the first N-channel MOSFET and a second terminal driven by a respective first digital signal switching between the reference voltage and a positive voltage supply, and a second capacitor with one terminal connected to the charge pump stage output terminal and a second terminal connected to a respective second digital signal switching between the reference voltage and the voltage supply. A gate electrode of the second N-channel MOSFET is connected, in the first stage, to a third digital signal switching between the reference voltage and the voltage supply, while in the remaining stage the gate electrode of the second N-channel MOSFET is connected to the stage input terminal.

NMOS negative charge pump

A charge pump comprises a plurality of stages connected in series, an input terminal of the charge pump being connected to a voltage supply and an output terminal of the charge pump providing an output voltage higher than the voltage supply. Each stage comprises unidirectional current flow MOS transistor means connected between a stage input terminal and a stage output terminal allowing current to flow only from said stage input terminal to said stage output terminal, and a first capacitor with one plate connected to said stage output terminal and another plate driven by a respective first digital signal periodically switching between ground and said voltage supply. The unidirectional current flow MOS transistor means of the stages have independent bulk electrodes, and a bias voltage generator circuit is provided for biasing the bulk electrodes of said unidirectional current flow MOS transistor means at respective bulk potentials which become progressively higher going from the stages proximate to said input terminal to the stages proximate to said output terminal of the charge pump.

Positive charge pump

A voltage regulator for memory circuits has a differential stage having a non-inverting input terminal receiving a control voltage independent of the temperature; an inverting input terminal connected to a ground voltage reference; a feed terminal connected to a booster circuit adapted for producing a boosted voltage; and an output terminal connected to an output terminal of the voltage regulator, for producing an output voltage reference starting from the comparison of input voltages. The voltage regulator further comprises a connecting transistor inserted between the feed terminal and the output terminal of the differential stage, the connecting transistor being source follower having a control terminal connected to the output terminal of the differential stage, as well as a source terminal connected to the output terminal of the voltage regulator, in such a way as to self-limit the transition of the voltage on the output terminal.

Voltage regulator for single feed voltage memory circuits, and flash type memory in particular

A charge pump comprises at least one charge pump stage including a first diode having an anode and a cathode, and a capacitor having a first plate connected to the cathode of the diode and a second plate connected to a clock signal that periodically varies between a reference voltage and a supply voltage, the anode of said diode forming a first terminal of the charge pump. The charge pump further comprises a second diode having an anode connected to the cathode of the first diode and a cathode forming a second terminal of the charge pump, first switching means for selectively coupling the first terminal of the charge pump to the voltage supply and second switching means for selectively coupling the second terminal of the charge pump to the reference voltage. The first switching means and the second switching means are respectively closed and open in a first operating condition whereby the second terminal of the charge pump acquires a voltage of the same polarity but higher in absolute value than said supply voltage. The first switching means and the second switching means are respectively open and closed in a second operating condition whereby the first terminal of the charge pump acquires a voltage of opposite polarity with respect to said voltage supply.

Bidirectional charge pump generating either a positive or negative voltage

A charge pump includes a plurality of stages connected in series between a reference potential and an output terminal of the charge pump. The plurality of stages includes a first group of stages, proximate to the reference potential, and a second group of stages proximate to the output terminal of the charge pump. Each stage of the first group includes a pass-transistor with first and second terminals respectively connected to an input and an output of the stage, and a first capacitor with a first plate connected to the output of the stage and a second plate driven by a digital signal switching between the reference voltage and a positive voltage. Each stage of the second group includes a junction diode having a first electrode connected to an input of the stage and a second electrode connected to an output of the stage, and a second capacitor having a first plate connected to the output of the stage and a second plate driven by a digital signal switching between the reference voltage and the voltage supply.

Jacopo Mulatti

Papers

NMOS negative charge pump

Positive charge pump

Voltage regulator for single feed voltage memory circuits, and flash type memory in particular

Bidirectional charge pump generating either a positive or negative voltage

BiCMOS negative charge pump