We propose a novel planning framework for the automated composition of web services We consider services that are specified and implemented in industrial standard languages for business processes modeling and execution, like BPEL4WS These languages describe web services whose behavior is intrinsically asynchronous For this reason, the key aspect of our framework is the modeling of asynchronous planning problems In the paper we describe the framework and propose a planning approach that is based on state of the art techniques for planning under uncertainty Our experiments show that this approach can scale up to significant cases, ie, to cases in which the manual development of BPEL4WS composed services is not trivial and is time consuming

Automated composition of web services by planning in asynchronous domains

The automatic synthesis of low power finite-state machines (FSM's) with gated clocks relies on efficient algorithms for synthesis and optimization of dedicated clock-stopping circuitry. We describe a new transformation for incompletely specified Mealy-type machines that makes them suitable for gated-clock implementation with a limited increase in complexity. The transformation is probabilistic-driven, and identifies highly-probable idle conditions that will be exploited for the optimal synthesis of the logic block that controls the local clock of the FSM. We formulate and solve a new logic optimization problem, namely, the synthesis of a subfunction of a Boolean function that is minimal in size under a constraint on its probability to be true. We describe the relevance of this problem for the optimal synthesis of gated clocks. A prototype tool has been implemented and its performance, although influenced by the initial structure of the FSM, shows that sizable power reductions can be obtained using our technique.

Automatic synthesis of low-power gated-clock finite-state machines

Two-level logic minimization: an overview

With the use of state and memory reduction techniques in verification by explicit state enumeration, runtime becomes a major limiting factor. We describe a parallel version of the explicit state enumeration verifier Murϕ for distributed memory multiprocessors and networks of workstations that is based on the message passing paradigm. In experiments with three complex cache coherence protocols, parallel Murϕ shows close to linear speedups, which are largely insensitive to communication latency and bandwidth. There is some slowdown with increasing communication overhead, for which a simple yet relatively accurate approximation formula is given. Techniques to reduce overhead and required bandwidth and to allow heterogeneity and dynamically changing load in the parallel machine are discussed, which we expect will allow good speedups when using conventional networks of workstations.

/pdf/parallelizing-the-murph-verifier-3bwytsk29u.pdf

Parallelizing the Murϕ verifier

With the use of state and memory reduction techniques in verification by explicit state enumeration, runtime becomes a major limiting factor. We describe a parallel version of the explicit state enumeration verifier Murp for distributed memory multiprocessors and networks of workstations using the message passing paradigm. In experiments with three complex cache coherence protocols on an Sp2 multiprocessor and on a network of workstations at UC Berkeley, parallel Murp shows close to linear speedups, which are largely insensitive to communication latency and bandwidth. There is some slowdown with increasing communication overhead, for which a simple yet relatively accurate approximation formula is given. Techniques to reduce overhead and required bandwidth and to allow heterogeneity and dynamically changing load in the parallel machine are discussed, which we expect will allow good speedups when using conventional networks of workstations.

Parallelizing the Murp Verifier

We present a new algorithm for exact two-level logic optimization which radically improves the Quine-McCluskey (QM) procedure. The new algorithm derives the covering problem directly and implicitly without generating the set of all prime implicants. It then generates only those prime implicants involved in the covering problem. We represent a set of primes by the cube of their intersection. Therefore, the unique set of sets of primes which forms the covering problem can be implicitly represented by a set of cubes which forms a minimum canonical cover. We obtain the minimum canonical cover starting from any initial cover and then derive the covering problem. The method is effective; it improves on the runtime and memory usage of ESPRESSO-EXACT by average factors of 1.78 and 1.19 respectively on the 114 of 134 benchmark examples that could be completed by ESPRESSO-EXACT. Of the remaining 20 hard problems, we solve 14 exactly. For 3 of the remaining 6 the covering problem is derived but it could not be solved exactly.

ESPRESSO-SIGNATURE: A New Exact Minimizer for Logic Functions

An algorithm for exact two-level logic optimization that radically improves the Quine-McCluskey (QM) procedure is presented. The new algorithm derives the covering problem directly and implicitly without generating the set of all prime implicants. It then generates only those prime implicants involved in the covering problem. A set of primes is represented by the cube of their intersection. Therefore, the unique set of sets of primes that forms the covering problem can be implicitly represented by a set of cubes that forms a minimum canonical cover. The minimum canonical cover starting from any initial cover is obtained and then the covering problem is derived. The method is effective; it improves on the runtime and memory usage of ESPRESSO-EXACT by average factors of 1.78 and 1.19, respectively, on the 114 of 134 benchmark examples that could be completed by ESPRESSO-EXACT. Of the remaining 20 hard problems, 14 are solved exactly. For three of the remaining six, the covering problem is derived but it can not be solved exactly. >

ESPRESSO-SIGNATURE: a new exact minimizer for logic functions

The success of binary decision diagram (BDD) based algorithms for verification depend on the availability of a high performance package to manipulate very large BDDs. State-of-the-art BDD packages, based on the conventional depth-first technique, limit the size of the BDDs due to a disorderly memory access patterns that results in unacceptably high elapsed time when the BDD size exceeds the main memory capacity. We present a high performance BDD package that enables manipulation of very large BDDs by using an iterative breadth-first technique directed towards localizing the memory accesses to exploit the memory system hierarchy. The new memory-oriented performance features of this package are: 1) an architecture independent customized memory management scheme, 2) the ability to issue multiple independent BDD operations (superscalarity), and 3) the ability to perform multiple BDD operations even when the operands of some BDD operations are the result of some other operations yet to be completed (pipelining). A comprehensive set of BDD manipulation algorithms are implemented using the above techniques. Unlike the breadth-first algorithms presented in the literature, the new package is faster than the state-of-the-art BDD package by a factor of up to 15, even for the BDD sizes that fit within the main memory. For BDD sizes that do not fit within the main memory, a performance improvement of up to a factor of 100 can be achieved.

/pdf/high-performance-bdd-package-by-exploiting-memory-hierarchy-2yb5eahrxd.pdf

High performance BDD package by exploiting memory hierarchy

The success of all binary decision diagram (BDD) based synthesis and verification algorithms depend on the ability to efficiently manipulate very large BDDs. We present algorithms for manipulation of very large Binary Decision Diagrams (BDDs) on a network of workstations (NOW). A NOW provides a collection of main memories and disks which can be used effectively to create and manipulate very large BDDs. To make efficient use of memory resources of a Now, while completing execution in a reasonable amount of wall clock time, extension of breadth-first technique is used to manipulate BDDs. BDDs are partitioned such that nodes for a set of consecutive variables are assigned to the same workstation. We present experimental results to demonstrate the capability of such an approach and point towards the potential impact for manipulating very large BDDs.

Binary decision diagrams on network of workstations

We present a new algorithm for exact two-level logic optimization. It differs from the classical approach; rather than generating the set of all prime implicants of a function, and then deriving a covering problem, we derive the covering problem directly and implicitly, and then generate only those primes involved in the covering problem. We represent a set of primes by the cube of their intersection. We then derive some properties of the sets of primes which form this set covering problem. We prove that the set of sets of primes which forms the covering problem for an incompletely-specified logic function.F. is unique. Hence the corresponding set of cubes forms a minimum canonical cover for F. We give a successive reduction algorithm for finding the minimum canonical cover from any initial cover. Using the minimum canonical cover, we then generate only those primes involved in at least one minimal cover of F. We discuss two related heuristic minimization procedures; a relaxed form of the exact procedure, and then an improved form of the ESPRESSO-II procedure. We give experimental results for the exact minimizer. The method is effective; solutions for 10 of the 20 hard examples in the ESPRESSO benchmark set are derived and proved minimum. In addition, for 5 of the remaining examples the minimum canonical cover is derived, but the covering problem remains to be solved exactly.

Jagesh V. Sanghavi

Papers

ESPRESSO-SIGNATURE: A New Exact Minimizer for Logic Functions

ESPRESSO-SIGNATURE: a new exact minimizer for logic functions

High performance BDD package by exploiting memory hierarchy

Binary decision diagrams on network of workstations

A New Exact Minimizer for Two-Level Logic Synthesis