In one embodiment, the present invention includes a processor having a plurality of cores and a control logic to control provision of a voltage/frequency to a first core of the plurality of cores independently of provision of a voltage/frequency to at least a second core of the plurality of cores In some embodiments, the voltages may be provided from one or more internal voltage regulators of the processor Other embodiments are described and claimed

Providing per core voltage and frequency control

In one embodiment, the present invention includes a method for providing power state change information from a plurality of cores of a processor to a predictor at a periodic interval and generating a prediction to indicate a predicted operation level of the cores during a next operating period Other embodiments are described and claimed

Predicting Future Power Level States For Processor Cores

A processor package is controlled to be in a package low power state for a first portion of an operation interval and in a package active state for a second portion of the operation interval. To enable the low power state, operations scheduled during the first portion are delayed until the second portion.

Transitioning a processor package to a low power state

In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed.

Dynamically allocating a power budget over multiple domains of a processor

Systems and methods of managing power provide for issuing a first operating requirement from a first processor core and issuing a second operating requirement from a second processor core. In one embodiment, the operating requirements can reflect either a power policy or a performance policy, depending upon the factor that is currently most important to software. Hardware coordination logic is used to coordinate a shared resource setting with the operating requirements. The hardware coordination logic is also able to coordinate the shared resource setting with independent resource settings of the first and second processor cores based on the operating requirements.

Power management coordination in multi-core processors

Some embodiments of the invention include a system and method for optimizing the latency of dynamic memory sizing. In some embodiments, the operating requirements can reflect amount of memory required to perform commensurate operations. Memory power management logic is used to coordinate memory requirements with operating requirements. The latency of changes to the memory based on operating requirements is optimized by the method and system. Other embodiments are described.

Method and system for optimizing latency of dynamic memory sizing

Embodiments are generally directed to providing power savings for a neural network architecture with zero activations during inference An embodiment of an apparatus includes one or more processors including one or more processor cores; and a memory to store data for processing including neural network processing, wherein the apparatus to perform a fast clear operation to initialize activation buffers for a neural network by updating metadata to indicate zero values, the neural network including a plurality of layers, wherein the apparatus is to compare outputs for the neural network to the metadata values and to write an output to memory only if the output is non-zero

Power savings for neural network architecture with zero activations during inference

Methods and apparatus relating to techniques for resource load balancing based on usage and/or power limits are described. In an embodiment, resource load balancing logic causes a first resource of a processor to operate at a first frequency and a second resource of the processor to operate at a second frequency. Memory stores a plurality of frequency values. The resource load balancing logic also selects the first frequency and the second frequency based on the stored plurality of frequency values. Operation of the first resource at the first frequency and the second resource at the second frequency in turn causes the processor to operate under a power budget. The resource load balancing logic causes change to the first frequency and the second frequency in response to a determination that operation of the processor is different than the power budget. Other embodiments are also disclosed and claimed.

Resource load balancing based on usage and power limits

Verfahren und System zum Optimieren der Latenz bei dynamischer Speichereinteilung

Dynamic power budget allocation in a multi-processor system is described. In an example, an apparatus includes a plurality of processor units; and a power control component, the power control component to monitor power utilization of each of the plurality of processor units, wherein power consumed by the plurality of processor units is limited by a global power budget. The apparatus is to assign a workload to each of the processor units and is to establish an initial power budget for operation of each of the processor units, and, upon the apparatus determining that one or more processor units require an increased power budget based on one or more criteria, the apparatus is to dynamically reallocate an amount of the global power budget to the one or more processor units.

Jahagirdar Sanjeev

Papers

Method and system for optimizing latency of dynamic memory sizing

Power savings for neural network architecture with zero activations during inference

Resource load balancing based on usage and power limits

Verfahren und System zum Optimieren der Latenz bei dynamischer Speichereinteilung

Dynamic power budget allocation in multi-processor system