Fault tolerant and redundant grand master clock scheme may reduce or eliminate precision time transition caused by a network link or device failure. A primary synchronization message may be sent by a primary grandmaster clock and one or more backup synchronization message may be sent by respective backup grandmaster clocks. The primary and backup grandmaster clocks may be concurrently operated. The primary and backup synchronization messages may be sent to an end station over a network. The end station may derive a local clock based on one, some, or all of the received messages. The end station may or may not distinguish between the messages based on the clock source. The end station may validate messages received from a particular clock source.

Fault tolerant clock network

Systems or methods of the present disclosure may provide high-bandwidth, low-latency connectivity for inter-die and/or intra-die communication of a modularized integrated circuit system. Such an integrated circuit system may include a first die of fabric circuitry sector(s), a second die of modular periphery intellectual property (IP), a passive silicon interposer coupling the first die to the second die, and a modular interface that includes a network-on-chip (NOC). The modular interface may provide high-bandwidth, low-latency communication between the first die and the second, between the fabric circuitry sector(s), and between the first die and a third die.

Network-on-chip for inter-die and intra-die communication in modularized integrated circuit devices

An apparatus relating generally to a transmitter-side of a transceiver or a transmitter used to provide a clock signal is disclosed. In this apparatus, a first signal source is to provide a first periodic signal. A second signal source is to provide a second periodic signal. A first multiplexer is coupled to receive the first periodic signal and the second periodic signal to provide a selected one thereof as a first selected output. A phase interpolator is coupled to the first multiplexer to receive the first selected output. The phase interpolator includes a second multiplexer. The second multiplexer is coupled to receive the first selected output and a phase-interpolated version of the first selected output to output a selected one thereof as a second selected output. A divider is coupled to the second multiplexer to receive the second selected output to provide the clock signal.

Transceiver for providing a clock signal

A memory system including a memory controller with channel interfaces connecting memory groups via channels Each channel interface communicates control, address and/or data (CAD) signals to a channel-connected memory group synchronously with a slave clock derived from an input clock The various slave clocks being uniquely generated by application of channel interface specific phase/frequency modulation or temporal delay, such that the respective CAD signals are characterized by skewed transition timing

Memory system with multiple channel interfaces and method of operating same

A circuit for transmitting data in an integrated circuit device is described. The circuit comprises a first data width conversion circuit configured to receive a first portion of transmit data to be transmitted in parallel; a first parallel-in, serial-out circuit configured to receive an output of the first data width conversion circuit; a first reset timer configured to provide a first reset signal to enable resetting the first data width conversion circuit; a second data width conversion circuit configured to receive a second portion of the transmit data; a second parallel-in, serial-out circuit configured to receive an output of the second data width conversion circuit; and a second reset timer configured to provide a second reset signal to enable resetting the second data width conversion circuit.

Circuits for and methods of transmitting data in an integrated circuit

A method of aligning clock signals in multiple transceiver channels on an integrated circuit may include adjusting a slave clock signal at a slave transceiver channel based on a master clock signal received from a master transceiver channel. A clock generation circuit and/or a delay circuit in the slave transceiver channel may be used to adjust the slave clock signal to produce an intermediate slave clock signal. The master clock signal may be adjusted based on the intermediate slave clock signal received at the master transceiver channel to obtain a total adjustment value. The phase of the intermediate slave clock signal may further be adjusted at the slave transceiver channel based on the total adjustment made at the master transceiver channel.

Methods and apparatus for aligning clock signals on an integrated circuit

An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.

Interface bridge between integrated circuit die

Systems and methods for reconfiguration of a hardened intellectual property (IP) block in an integrated circuit (IC) device are provided. Reconfiguration of the hardened IP block in the IC device may transition between functions supported by the hardened IP block. A transition may occur as a pre-configured profile is selected to reconfigure the hardened IP block. Further, configuration data associated with each of the pre-configured profiles of the hardened IP block may be generated and storage space to store the configuration data may be created. Additionally, reconfiguration control logic to read and implement the configuration data in hard IP design primitives may also be generated.

Selectable reconfiguration for dynamically reconfigurable IP cores

A computer-implemented method includes receiving a first circuit design for an integrated circuit device, determining when multiple power-drawing events are to occur at substantially the same time via one or more circuitry components of the integrated circuit device, which would have a disruptive effect on a power distribution network of the integrated circuit device, based on the first circuit design, and generating logic that schedules the more than one event so that the more than one event do not occur simultaneously The logic is included in an event sequencer The method also includes inserting the event sequencer into the first circuit design during compilation to create a second circuit design and outputting the second circuit design to be implemented on the integrated circuit device

Reset Sequencing for Reducing Noise on a Power Distribution Network

Techniques and mechanisms allow for implementing multiple configuration profiles for dynamic reconfiguration of an Intellectual Property (IP) core. A minimum set of data may be generated, as well as detecting errors between the configuration profiles.

Jakob Raymond Jones

Papers

Methods and apparatus for aligning clock signals on an integrated circuit

Interface bridge between integrated circuit die

Selectable reconfiguration for dynamically reconfigurable IP cores

Reset Sequencing for Reducing Noise on a Power Distribution Network

Multiple reconfiguration profiles for dynamically reconfigurable intellectual property cores