A computer data storage device made up of both solid state storage and rotating magnetic disk storage maintains a fast response time approaching that of a solid state device for many workloads and improves on the response time of a normal magnetic disk for practically all workloads. The high performance is accomplished by a special hardware configuration coupled with unique procedures and algorithms for placing and maintaining data in the most appropriate media based on actual and projected activity. The system management features a completely searchless method (no table searches) for determining the location of data within and between the two devices. Sufficient solid state memory capacity is incorporated to permit retention of useful, active data, as well as to permit prefetching of data into the solid state storage when the probabilities favor such action. Movement of updated data from the solid state storage to the magnetic disk and of prefetched data from the magnetic disk to the solid state storage is done on a timely, but unobtrusive, basis as background tasks of the described device. A direct, private channel between the solid state storage and the magnetic disk prevents the conversations between these two media from conflicting with the transmission of data between the host computer and the described device. A set of microprocessors manages and oversees the data transmission and storage. Data integrity is maintained through a power interruption via a battery assisted, automatic and intelligent shutdown procedure.

Method of operating a cache memory including determining desirability of cache ahead or cache behind based on a number of available I/O operations

Solid-state flash electrically erasable and programmable read-only-memory ("flash EEPROM") system is combined with a rotating disk drive memory to provide mass program and data storage in a computer system. A common memory controller directs system generated memory addresses in a disk format to either the EEPROM system or disk memory. The blocks of data handled by the EEPROM system have the same size and other attributes as sectors of data handled by the disk system, thereby making it transparent to the computer system processor as to whether it is accessing the EEPROM or disk portion of the storage system. A particular program or data file may then be stored in the portion of the memory system best suited to handle it, and thus take advantage of the different features and characteristics of EEPROM and magnetic media disk memory.

Mass computer storage system having both solid state and rotating disk types of memory

Cache flushing is effected for a flash memory by copying, to a block of the memory, first and second portions of cached data, and servicing a host access in-between copying the first portion and the second portion. Either both portions are selected before the copying, or erasing the block is forbidden until after the copying, or a portion of the block left unwritten by the first copying remains unwritten until after the host access is serviced.

Interruptible cache flushing in flash memory systems

A system is described wherein a CPU, a main memory means and a bus means are provided. Cache memory means is employed to couple the CPU to the bus means and is further provided with means to indicate the status of a data unit stored within the cache memory means. One status indication tells whether the contents of a storage position have been modified since those contents were received from main memory and another indicates whether the contents of the storage position may be present elsewhere memory means. Control means are provided to assure that when a data unit from a CPU is received and stored in the CPU's associated cache memory means, which data unit is indicated as being also stored in a cache memory means associated with another CPU, such CPU data unit is also written into main memory means. During that process, other cache memory means monitor the bus means and update its corresponding data unit. Bus monitor means are provided and monitor all writes to main memory and reads from main memory to aid in the assurance of system-wide data integrity.

Multi-processor system with cache memories

This disclosure describes a snooping coherency protocol for a multiprocessor network wherein every processor has its own private cache and bus interface means and the network is connected via a common system bus. Each processor has its own cache directory and image directory that duplicate each other non-atomically. The snooping protocol utilizes the duality of directories coupled with the non-atomicity of directory updates to maximize processor-cache availability and minimize processor-cache access times thus supporting high performance architectures.

Hardware implemented cache coherency protocole with duplicated distributed directories for high-performance multiprocessors

A system for maintaining data consistency among distributed processors, each having its associated cache memory. A processor addresses data in its cache by specifying the virtual address. The cache will search its cells for the data associatively. Each cell has a virtual address, a real address, flags and a plurality of associated data words. If there is no hit on the virtual address supplied by the processor, a map processor supplies the equivalent real address which the cache uses to access the data from another cache if one has it, or else from real memory. When a processor writes into a data word in the cache, the cache will update all other caches that share the data before allowing the write to the local cache.

James A. Steffen

Papers

Virtual memory cache for use in multi-processing systems