An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

An active matrix display device having a pixel structure in which pixel electrodes, gate wirings and source wirings are suitably arranged in the pixel portions to realize a high numerical aperture without increasing the number of masks or the number of steps. The device comprises a gate electrode and a source wiring on an insulating surface, a first insulating layer on the gate electrode and on the source wiring, a semiconductor layer on the first insulating film, a second insulating layer on the semiconductor film, a gate wiring connected to the gate electrode on the second insulating layer, a connection electrode for connecting the source wiring and the semiconductor layer together, and a pixel electrode connected to the semiconductor layer.

Semiconductor Device and Method of Fabricating the Same

Surgical clips, and methods of use thereof, are provided for tissue approximation and attachment, and more particularly, for sealingly joining a graft vessel to a target vessel. The graft vessel has a free end and a graft vessel wall defining a graft lumen. The target vessel has a target vessel wall defining a target lumen and has an opening in the target vessel wall. The anastomosis clip includes a clip body having a distal extremity with a distal end and a proximal extremity with a proximal end. The distal end is configured to penetrate through the graft vessel wall near the free end and through the target vessel wall near the opening such that both the distal and proximal ends of the clip body are outside the graft and target vessels. At least a portion of the clip body is shapable so as to compress the graft vessel wall against the target vessel wall with the target vessel lumen in communication with the graft vessel lumen.

Surgical clips and methods for tissue approximation

An RF switch circuit and method for switching RF signals that may be fabricated using common integrated circuit materials such as silicon, particularly using insulating substrate technologies. The RF switch includes switching and shunting transistor groupings to alternatively couple RF input signals to a common RF node, each controlled by a switching control voltage (SW) or its inverse (SW_), which are approximately symmetrical about ground. The transistor groupings each comprise one or more insulating gate FET transistors connected together in a “stacked” series channel configuration, which increases the breakdown voltage across the series connected transistors and improves RF switch compression. A fully integrated RF switch is described including control logic and a negative voltage generator with the RF switch elements. In one embodiment, the fully integrated RF switch includes an oscillator, a charge pump, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit.

Switch Circuit and Method of Switching Radio Frequency Signals

An integrated deposition system is described that is capable of vaporizing low vapor pressure liquid precursors and conveying the vapor to a processing region to fabricate advanced integrated circuits. The integrated deposition system includes a heated exhaust system, a remote plasma generator, a processing chamber, a liquid delivery system, and a computer control module that together create a commercially viable and production worthy system for depositing high capacity dielectric materials from low vapor pressure precursors.

Apparatus for the deposition of high dielectric constant films

Low threshold voltage MOS devices having buried electrodes (46) are disclosed herein. Such devices have source and drain regions which include tip regions (36A, 38A) and plug regions (36, 38). The buried electrodes (46) have bottom boundaries located above the bottoms of the plug regions (36, 38). The buried electrode (46) has the same conductivity type as the device's bulk (albeit at a higher dopant concentration) and, of course, the opposite conductivity type as the device's source and drain. The exact dopant concentrations and locations of the buried electrodes (46) should be provided such that punch through is avoided in MOS devices.

Low threshold voltage, high performance junction transistor

To reduce threshold levels in fully depleted SOI devices having back gate wells, the channel regions of the devices are formed of an intrinsic or pseudo-intrinsic semiconductor. Also, multiple well structures or isolation regions are formed below the oxide layer to reduce diode junction leakage between the back gate wells of the devices.

Tunable threshold SOI device using isolated well structure for back gate

Disclosed is a low threshold asymmetric MOS device having a pocket region with a graded concentration profile. The pocket region includes a relatively high dopant atom concentration (of the same conductivity type as the bulk region) abutting either the device's source or its drain along the side of the source or drain that faces the device's channel region. The pocket region's graded concentration profile provides a lower dopant concentration near the substrate surface and an increasing dopant concentration below that surface. This provides a relatively low resistance conduction path through the pocket region, while allowing the device's threshold voltage to be somewhat higher at the pocket region. The asymmetric device can also include a counter dopant region located beneath its substrate surface. This forces current to flow in the substrate but just above the region of high counter dopant concentration, where the resistance is relatively low.

Method for forming MOS devices with retrograde pocket regions and counter dopant regions at the substrate surface

Low threshold voltage MOS devices having asymmetric halo implants are disclosed herein. An asymmetric halo implant provides a pocket region located under a device's source or drain near where the source (or drain) edge abuts the device's channel region. The pocket region has the same conductivity type as the device's bulk (albeit at a higher dopant concentration) and, of course, the opposite conductivity type as the device's source and drain. Only the source or drain, not both, have the primary pocket region. An asymmetric halo device behaves like two pseudo-MOS devices in series: a "source FET" and a "drain FET." If the pocket implant is located under the source, the source FET will have a higher threshold voltage and a much shorter effective channel length than the drain FET.

Method of making asymmetric low power MOS devices

Buried platform wells are specifically used to electrically interact with the platform transistors of the invention. The dopant concentration distribution of the buried platform wells is used to change the threshold voltage of the platform transistors of the invention by introducing a tail dopant concentration into the active region of the platform transistors. The platform transistors of the invention can also be used in conjunction with standard transistors, on a single structure, to provide both low and relatively high threshold voltage transistors on a single structure. Consequently, using the method and structure of the invention, considerable versatility and design flexibility are achieved with minimum additional structural complexity.

James B. Burr

Papers

Low threshold voltage, high performance junction transistor

Tunable threshold SOI device using isolated well structure for back gate

Method for forming MOS devices with retrograde pocket regions and counter dopant regions at the substrate surface

Method of making asymmetric low power MOS devices

Method for engineering the threshold voltage of a device using buried wells