A re-programmable non-volatile memory system, such as a flash EEPROM system, having its memory cells grouped into blocks of cells that are simultaneously erasable is operated in a manner to level out the wear of the individual blocks through repetitive erasing and re-programming. This may be accomplished without use of counts of the number of times the individual blocks experience erase and re-programming but such counts can optionally aid in carrying out the wear leveling process. Individual active physical blocks are chosen to be exchanged with those of an erased block pool in a predefined order.

Cyclic flash memory wear leveling

A re-programmable non-volatile memory system, such as a flash EEPROM system, having its memory cells grouped into blocks of cells that are simultaneously erasable is operated to perform memory system housekeeping operations in the foreground during execution of a host command, wherein the housekeeping operations are unrelated to execution of the host command. Both one or more such housekeeping operations and execution of the host command are performed within a time budget established for executing that particular command. One such command is to write data being received to the memory. One such housekeeping operation is to level out the wear of the individual blocks that accumulates through repetitive erasing and re-programming.

Scheduling of housekeeping operations in flash memory systems

Techniques for the management of spare blocks in re-programmable non-volatile memory system, such as a flash EEPROM system, are presented. In one set of techniques, for a memory partitioned into two sections (for example a binary section and a multi-state section), where blocks of one section are more prone to error, spare blocks can be transferred from the more error prone partition to the less error prone partition. In another set of techniques for a memory partitioned into two sections, blocks which fail in the more error prone partition are transferred to serve as spare blocks in the other partition. In a complementary set of techniques, a 1-bit time stamp is maintained for free blocks to determine whether the block has been written recently. Other techniques allow for spare blocks to be managed by way of a logical to physical conversion table by assigning them logical addresses that exceed the logical address space of which a host is aware.

Spare block management in non-volatile memories

A non-volatile memory system is organized in physical groups of physical memory locations. Each physical group (metablock) is erasable as a unit and can be used to store a logical group of data. A memory management system allows for update of a logical group of data by allocating a metablock dedicated to recording the update data of the logical group. The update metablock records update data in the order received and has no restriction on whether the recording is in the correct logical order as originally stored (sequential) or not (chaotic). Eventually the update metablock is closed to further recording. One of several processes will take place, but will ultimately end up with a fully filled metablock in the correct order which replaces the original metablock. In the chaotic case, directory data is maintained in the non-volatile memory in a manner that is conducive to frequent updates. The system supports multiple logical groups being updated concurrently.

Non-volatile memory and method with block management system

In a nonvolatile memory with block management system that supports update blocks with non-sequential logical units, an index of the logical units in a non-sequential update block is buffered in RAM and stored periodically into the non-volatile memory. In one embodiment, the index is stored in a block dedicated for storing indices. In another embodiment, the index is stored in the update block itself. In yet another embodiment, the index is stored in the header of each logical unit. In another aspect, the logical units written after the last index update but before the next have their indexing information stored in the header of each logical unit. In this way, after a power outage, the location of recently written logical units can be determined without having to perform a scanning during initialization. In yet another aspect, a block is managed as partially sequential and partially non-sequential, directed to more than one logical subgroup.

Non-volatile memory and method with non-sequential update block management

The present invention provides a flash memory management system and method with increased performance. The flash memory management system provides the ability to efficiently manage and allocate flash memory use in a way that improves reliability and longevity, while maintaining good performance levels. The flash memory management system includes a free block mechanism, a disk maintenance mechanism, and a bad block detection mechanism. The free block mechanism provides efficient sorting of free blocks to facilitate selecting low use blocks for writing. The disk maintenance mechanism provides for the ability to efficiently clean flash memory blocks during processor idle times. The bad block detection mechanism provides the ability to better detect when a block of flash memory is likely to go bad. The flash status mechanism stores information in fast access memory that describes the content and status of the data in the flash disk. The new bank detection mechanism provides the ability to automatically detect when new banks of flash memory are added to the system. Together, these mechanisms provide a flash memory management system that can improve the operational efficiency of systems that utilize flash memory.

Flash memory management system and method

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Flash memory management system and method utilizing multiple block list windows

An error response test system and method with increased functionality and improved performance is provided. The error response test system provides the ability to inject errors into the application under test to test the error response of the application under test in an automated and efficient manner. The error response test system injects asynchronous errors into the application under test by inserting code sequences of application code that are desired to create an error in the application under test. The error response test system inserts the error creation code directly into the object of the application under test. The inserted error creation code causes an error in the application under test at the specific point of insertion. The error creation code is designed to implement asynchronous errors that cannot normally be tested. Furthermore, the error creation code can be inserted in any location in the application under test. Thus, the application under test can be thoroughly tested for asynchronous error response.

System and method for testing response to asynchronous system errors

L'invention concerne un procede et un systeme de gestion de memoire flash aux performances ameliorees. Le systeme de gestion de memoire flash selon l'invention permet de gerer et de definir efficacement l'utilisation de la memoire flash d'une maniere ameliorant la fiabilite et la longevite tout en conservant de bons niveaux de performance. Le systeme de gestion de memoire flash selon l'invention comprend un mecanisme pour blocs libres, un mecanisme de maintenance de disque, ainsi qu'un mecanisme de detection de blocs defectueux. Le mecanisme pour blocs libres assure un tri efficace des blocs libres afin de faciliter la selection de blocs faiblement utilises pour l'ecriture. Le mecanisme de maintenance de disque est capable de nettoyer efficacement les blocs de memoire flash pendant les temps d'inactivite du processeur. Le mecanisme de detection de blocs defectueux sert a mieux detecter un bloc de memoire flash qui risque de devenir defectueux. Le mecanisme d'etat de memoire flash stocke dans la memoire a acces rapide des informations decrivant le contenu et l'etat des donnees sur le disque flash. Le mecanisme de detection de nouveaux blocs est capable de detecter automatiquement lorsque de nouveaux blocs de memoire flash sont ajoutes au systeme. Ensemble, ces mecanismes fournissent un systeme de gestion de memoire flash qui peut ameliorer l'efficacite operationnelle de systemes utilisant de la memoire flash.

James Chow

Papers

Flash memory management system and method

Flash memory management system and method utilizing multiple block list windows

System and method for testing response to asynchronous system errors

Procede et systeme de gestion de memoire flash