A new technique for computing the cube of an operand of any length is proposed, implemented, analyzed, and compared to existing techniques. The new proposed method is faster than previously proposed methods that compute the cube of an operand in parallel with the disadvantage that more counters are utilized to perform partial product reduction. Cubing circuits using the proposed techniques are implemented with several operand lengths and analyzed with regard to area consumption and latency. Results are shown for several designs in AMI C5N 0.6 mum technology

Partial Product Reduction for Parallel Cubing

In Very Large Scale Integration (VLSI) designs, Parallel prefix adders (PPA) have the better delay performance. This paper investigates four types of PPA’s (Kogge Stone Adder (KSA), Spanning Tree Adder (STA), Brent Kung Adder (BKA) and Sparse Kogge Stone Adder (SKA)). Additionally Ripple Carry Adder (RCA), Carry Look ahead Adder (CLA) and Carry Skip Adder (CSA) are also investigated. These adders are implemented in verilog Hardware Description Language (HDL) using Xilinx Integrated Software Environment (ISE) 13.2 Design Suite. These designs are implemented in Xilinx Spartan 6 Field Programmable Gate Arrays (FPGA). Delay and area are measured using XPower analyzer and all these adder’s delay, power and area are investigated and compared finally.

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Design and Estimation of delay, power and area for Parallel prefix adders

Estimating arithmetic is a design paradigm for DSP hardware. By allowing structurally incomplete arithmetic circuits to occasionally perform imprecise calculations, higher performance can be achieved in many different electronic systems. By means of approximate compressor design and bottom-up tree topology, this paper presents a novel approach of implementing high-speed, area-efficient and power-aware multipliers. Experimental results are given to show the applicability and effectiveness of our proposed approach.

High-speed area-efficient and power-aware multiplier design using approximate compressors along with bottom-up tree topology

According to dramatically growing interesting in power-efficient embedded processor, designers must establish the proper power strategy when they design new embedded processor cores. This paper develops a SPARC compatible floating-point co-processor, which is part of a SPARC compatible embedded processor and implements the SPARC V8 floating-point instruction set except for square root and all quad precision instructions. To lower the power dissipation of floating-point co-processor, we modify the decoder stage of the integer unit pipeline to generate the clock gating signals so that the unused floating-point co-processor execution pipeline can be clock-gated. The design is implemented in a SMIC 0.18-mum CMOS process.

A Power-Efficient Floating-Point Co-processor Design

In this work we have proposed an efficient parallel prefix adder (PPA) that is a variation of the popular Brent-Kung PPA. In this proposed adder, with a glance on the sklansky adder and by varying the graph topology, we have reduced the number of stages in the critical delay path in comparison with Brent-Kung PPA and so lowered the delay. This advantage is along with a little increase in power consumption and area due to increasing the cells number so that the consequent Power Delay Product (PDP) is improved. Also the performance of our proposed PPA increases by increasing the input bits number from 32 bits up to higher orders. The experimental results indicate that our proposed adder is faster than the Brent-Kung adder by 10.1% in 32 bits, 17.2% in 64 bits and 21.3% in 128 bits and the consequent PDP is reduced by 8.8% in 32 bits, 15.6% in 64 bits and 19.5% in 128 bits. Circuit level simulations were performed with SPICE and CMOS 90nm technology.

A new parallel prefix adder structure with efficient critical delay path and gradded bits efficiency in CMOS 90nm technology

Preface. 1. Motivation. 2. Verilog at the RTL Level. 3. Addition. 4. Multiplication. 5. Division Using Recurrence. 6. Elementary Functions. 7. Division and Square Root Using Multiplicative-Based Methods. References. Index.

James E. Stine

Papers

Digital Computer Arithmetic Datapath Design Using Verilog HDL (International Series in Operations Researchand Management Science)