Aspects of compensating for transmitter output power may comprise sampling an on-chip transmitter circuit temperature at various time instants and determining a feedback temperature compensation value. At least one digital-to-analog converter may be adjusted by utilizing the feedback temperature compensation value, which may correspond to the sampled temperature. The digital-to-analog converter may be an I-component digital-to-analog converter and/or a Q-component digital-to-analog converter. At least a portion of the on-chip transmitter circuit may be characterized to determine power output dependence of the on-chip transmitter circuit on temperature variation of the on-chip transmitter circuit. Based on this characterization, a feedback temperature compensation value that may correspond to the sampled temperature may be used to adjust the digital-to-analog converter. The feedback temperature compensation value may be, for example, from a lookup table or an algorithm.

Method and system for transmitter output power compensation

A method and a device for noise processing are provided, the method comprising the steps of (i) data is transmitted from at least one transmitter to at least one receiver; and (ii) the at least one receiver conveys SNR-data, e.g., link state information and/or link quality information to a precoder and/or to a noise canceller.

Method and device for data processing and communication system comprising such device

Semiconductor methods and device structures for suppressing latch-up in bulk CMOS devices. The method comprises forming a trench in the semiconductor material of the substrate with first sidewalls disposed between a pair of doped wells, also defined in the semiconductor material of the substrate. The method further comprises forming an etch mask in the trench to partially mask the base of the trench, followed by removing the semiconductor material of the substrate exposed across the partially masked base to define narrowed second sidewalls that deepen the trench. The deepened trench is filled with a dielectric material to define a trench isolation region for devices built in the doped wells. The dielectric material filling the deepened extension of the trench enhances latch-up suppression.

Methods for fabricating semiconductor device structures with reduced susceptibility to latch-up and semiconductor device structures formed by the methods

A calibration unit is designed to contain an oscillator circuit whose frequency is determined by the RC time constant of a resistor, which is of the same type as the resistor used in the filter circuit that is to be calibrated, and of a capacitor device which has been set to a fixed value. The oscillator frequency is converted into counting pulses, and the number of counting pulses which is counted in a modulo binary counter within a time interval is transmitted as a digital calibration signal for a calibratable capacitor device in the filter circuit in order to calibrate the latter.

Device and method for calibrating R/C filter circuits

This paper presents a highly optimized quad analog front end (AFE) with integrated filters. With only firmware programming, this device supports VDSL, ADSL, HS-ADSL, and G.SHDSL as well as GlobeSpanVirata's proprietary DSL. This device is integrated in a 0.35/0.5 /spl mu/m CMOS process and its power dissipation scales as a function of the application requirements. With filter blocks activated and data converters clocked at 17.664 Mhz, the power dissipation is /spl les/ 350 mW per channel. This device has been used in systems.

A universal quad AFE with integrated filters for VDSL, ADSL, and G.SHDSL

An analog front-end circuit and method that supports multiple digital subscriber line (DSL) standards, including asymmetric digital subscriber line (ADSL) and very-high speed digital subscriber line (VDSL) is disclosed. The circuit incorporates multiple circuit blocks that can be selectively included into the transmit and receive paths of a DSL signal. It also permits selectable gain settings for signal amplifiers, and frequency bandwidth for signal filters that may be included in the transmit and receive paths. The receive path includes an analog-to-digital converter (ADC) that operates close to and exceeds the Nyquist sampling rate.

Wide-band analog front-end for DSL applications

A system and method for a filter tuner is presented. The system comprises a sequential logic, a register, a comparator, a first and second counter, a synchronizing logic, a first and second oscillator, a control logic, and a first and second combinational logic. The method comprises the steps of executing a calibration cycle of a filter tuner, executing a measurement cycle of the filter tuner, and tuning a filter with the filter tuner dependent on a determined cutoff frequency variation.

James J. Zhao

Papers

Wide-band analog front-end for DSL applications

Filter tuner system and method