An adaptive interface for a programmable system, for predicting a desired user function, based on user history, as well as machine internal status and context. The apparatus receives an input from the user and other data. A predicted input is presented for confirmation by the user, and the predictive mechanism is updated based on this feedback. Also provided is a pattern recognition system for a multimedia device, wherein a user input is matched to a video stream on a conceptual basis, allowing inexact programming of a multimedia device. The system analyzes a data stream for correspondence with a data pattern for processing and storage. The data stream is subjected to adaptive pattern recognition to extract features of interest to provide a highly compressed representation that may be efficiently processed to determine correspondence. Applications of the interface and system include a video cassette recorder (VCR), medical device, vehicle control system, audio device, environmental control system, securities trading terminal, and smart house. The system optionally includes an actuator for effecting the environment of operation, allowing closed-loop feedback operation and automated learning.

Adaptive pattern recognition based control system and method

This is achieved in a computer system employing a multiple facility operating system architecture. The computer system includes a plurality of processor units for implementing a predetermined set of peer-level facilities wherein each peer-level facility includes a plurality of related functions and a communications bus for interconnecting the processor units. Each of the processor units includes a central processor and the stored program that, upon execution, provides for the implementation of a predetermined peer-level facility of the predetermined set of peer-level facilities, and for performing a multi-tasking interface function. The multi-tasking interface function is responsive to control messages for selecting for execution functions of the predetermined peer-level facility and that is responsive to the predetermined peer-level facility for providing control messages to request or to respond to the performance of functions of another peer-level facility of the computer system. The multi-tasking interface functions of each of the plurality of processor units communicate among one another via the network bus.

Multiple software-facility component operating system for co-operative processor control within a multiprocessor computer system

A programmable interface for a peripheral circuit card is provided. The card is intended for use with a particular computer bus architecture, and the interface can be customized by a user for a particular card design. Instead of designing a custom interface chip, the designer can program one or more programmable logic devices on the interface chip to interface with whatever devices are on the peripheral circuit card.

Programmable interface for computer system peripheral circuit card

A bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces are provided for form an hierarchical serial bus assembly for serially interfacing a number of isochronous and asynchronous peripherals to the system unit of a computer system. The bus controller, bus signal distributors, and bus interfaces are provided with circuitry and complementary logic for implementing a master/slave model of flow control for serially interfacing the bus agents to each other to conduct data communication transactions. In certain embodiments, these circuitry and complementary logic further conduct connection management transactions employing also the master/slave model of flow control, implement a frame based polling schedule for polling the slave "devices", employ at least two address spaces to conduct the various transactions, support communication packet based transactions, and/or electrically represent data and/or control states.

System having independently addressable bus interfaces coupled to serially connected multi-ported signal distributors generating and maintaining frame based polling schedule favoring isochronous peripherals

A data processing system includes a planar board having a central processing unit (CPU), a main memory unit, and input/output (I/O) sockets or slots, each adapted to receive a selected one of a plurality of different and/or similar option cards. Each card contains (or is connected to) and controls a respective peripheral device; and each card is pre-wired with an ID value corresponding to its card type. Software programmable option registers on each card store parameters such as designated default (or alternate) address information, priority levels, and other system resource parameters. A setup routine, during initial power-on, retrieves and stores the appropriate parameters in the I/O cards and also in slot positions in main memory, one position being assigned to each slot on the board. Each slot position is adapted to hold the parameters associated with the card inserted in its respective slot and the card ID value. That portion of main memory containing the slot positions is adapted to maintain the parameter and ID information by means of battery power when system power fails or is disconnected, i.e., a nonvolatile memory portion. Subsequent power-on routines are simplified by merely transferring parameters from the table to the card option registers if the status of all the slots has not not changed since the last power-down, system reset, or channel reset.

Method and apparatus for automatic initialization of pluggable option cards

A computer system that is operable with any multiplexed-address memory (200) within a size range of 2N to 2N+R memory locations (211). The system has a memory of 2S locations selected from the predetermined range, and the memory has S/2 multiplexed address input terminals (231). Address bits forming a memory address, generated for example by a processor (400), are multiplexed by a memory controller (300) onto N/2 + R address output terminals (314) in two sets of N/2 + R address bits. The address bit sets have at least R/2 bits in common. An address bus (250) transports the multiplexed address bits to the memory. The bus has N/2 + R address leads (251) connected to the output terminals of the memory controller. S/2 of those address leads are also connected to the address input terminals of the memory. The remaining address leads are not connected. The memory controller multiplexes the address of any memory within the predetermined range onto its output terminals. Addressing of a different-size memory requires merely connecting the memory to the appropriate address leads of the multiplexed-address bus.

Multiplexed-address interface for addressing memories of various sizes

A multiprocessor system comprises a plurality of stations interconnected by a system communication bus and cooperating in the performance of system tasks. Each station includes a plurality of addressable elements interconnected by a station communication bus. All stations are mapped into a common address space, with the elements of each station mapped onto like relative addresses in two subspaces of the address space: a subspace which is shared in common by all stations, and a subspace dedicated to the station whose addresses are the common subspace addresses in combination with a station-identifying address portion. The stations are symmetrical: like elements in all of the stations are mapped onto like relative addresses in their associated subspaces. Addressing within the system is self-referential: a station accesses one of its addressable elements by placing its common subspace address on the station communication bus. Each station's station bus is selectively interfaced to the system bus, and a station accesses an addressable element of another station by placing its dedicated subspace address on the station bus, interfacing its station bus with the system bus, and causing the other station to interface its station bus with the system bus. A station accesses an element of another station passively, without utilizing the intelligence, if any, of the other station to make the access.

James Michael Grinn

Papers

Multiplexed-address interface for addressing memories of various sizes

Multiprocessor computing system featuring shared global control