A microcontroller with a mixed analog/digital architecture including multiple digital programmable blocks and multiple analog programmable blocks in a communication array having a programmable interconnect structure. The single chip design is implemented by integration of programmable digital and analog circuit blocks that are able to communicate with each other. Robust analog and digital blocks that are flash memory programmable can be utilized to realize complex design applications that otherwise would require multiple chips and/or separate applications. The programmable chip architecture includes a novel array having programmable digital blocks that can communicate with programmable analog blocks using a programmable interconnect structure. The programmable analog array contains a complement of Continuous Time (CT) blocks and a complement of Switched Capacitor (SC) blocks that can communicate together. The analog blocks consist of multi-function circuits programmable for one or more different analog functions, and fixed function circuits programmable for a fixed function with variable parameters. The digital blocks include standard multi-function circuits and enhanced circuits having functions not included in the standard digital circuits. The programmable array is programmed by flash memory and programming allows dynamic reconfiguration. That is, “on-the-fly” reconfiguration of the programmable blocks is allowed. The programmable analog array with both Continuous Time analog blocks and Switched Capacitor analog blocks are offered on a single chip along with programmable digital blocks. The programmable interconnect structure provides for communication of input/output data between all analog and digital blocks.

Programmable microcontroller architecture(mixed analog/digital)

Example embodiments of the present invention relate and a method and an apparatus for managing a short hash handle. The method including receiving an I/O including a first identifier for a data block and examining the first identifier in comparison with a second identifier. The data block identified in the I/O then may be managed according to the first identifier and the second identifier.

Method and apparatus for creating a short hash handle highly correlated with a globally-unique hash signature

Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.

Microcontroller Programmable System on a Chip

One disclosed system and method enables dynamic reconfiguration of an electronic device in association with testing activities in a convenient and efficient manner. In one implementation, the electronic device includes a bus for communicating information, a microprocessor for processing data, a programmable functional component including a plurality of functional blocks programmable to provide a plurality of functions and configurations, and a memory for storing instructions including instructions for causing the programmable functional component to change functions and configurations. The components are programmably configurable to perform a variety of functions. In one example, the memory stores a plurality of configuration images that define the configuration and functionality of the circuit. The information stored in the memory facilitates dynamic reconfiguration of the circuit in accordance with the test harness instructions. Based upon a command from a test computer, the electronic device is automatically reconfigured by the test harness activating different configuration images.

Reconfigurable testing system and method

An input/output (“I/O”) system includes a plurality of input/output (“I/O”) ports, measurement circuitry, and an I/O multiplexer bus. The measurement circuitry is coupled to measure one or more electrical properties of one or more devices to be externally coupled to one or more of the I/O ports. The I/O multiplexer bus is coupled between the I/O ports and the measurement circuitry. The I/O multiplexer bus is programmable to selectively couple the measurement circuitry to any of the I/O ports.

Input/output multiplexer bus

A multiple bus architecture for a system on a chip including bridges for decoupling clock frequencies of individual bus masters from peripherals they are accessing. Each bridge interfaces to all bus masters in the system that require access to the peripherals it interfaces to.

Bus architecture for system on a chip

Pre-configuration of a programmable device permits implementation and operation of the device using a first, dedicated operation usable upon power up of the programmable device without the need for programming the device using external configuration data. Configuration data can be provided in any suitable manner to re-configure the device to perform a second, programmable operation. The pre-configured design preferably uses programmable resources and leaves dedicated resources undisturbed during both first and second operations.

Functional pre-configuration of a programmable logic device

Embodiments of the present invention provide methods of reading data from and writing data to a memory, computer program products for performing such methods, and apparatus for reading data from and writing data to, a memory, which apparatus may be implemented, for example, as a Field Programmable Gate Array (FPGA). A key associated with data to be read from or written to the memory is converted into two separate values, which values are themselves converted into first and second index values, each having an associated signature value. The index values are used as indices to a signature table containing a signature value for each data entry stored in the memory from which data is to be read or to which data is to be written. In a read operation, a signature of the signature table which matches one of the signature values derived from the key is identified and a read address is calculated based on the index value associated with the matching signature value derived from the key. In a write operation, a signature value is written to the signature table at an address corresponding to one of the index values derived from the key, and a write address is calculated based on that index value.

Memory access system

A receiving device oversamples incoming serial data using multiple phases of its system clock. The device detects an initial edge in the set of samples and selects a sample based on the location of the initial edge. A first bit is set to the value of the selected sample. A portion of the set of samples following the initial edge. If an edge is detected, then a sample is selected based upon the location of the detected edge and the next bit is set to the value of the selected sample. If an edge is not detected within this portion, then the position of the next edge is estimated. A sample is selected based upon the location of the estimated edge and the next bit is set to the value of the selected sample. The analysis is repeated for another portion of the set of samples following the newest edge.

Efficient data recovery algorithm for serial data

A programmable logic device is reconfigurable between two functionalities, while it is in use. The programmable logic device has a first store, into which configuration data may be downloaded from an external memory device, and a second store, in which a copy of the configuration data is maintained, with the functionality of the programmable logic device being determined by the copy of the configuration data, thereby allowing additional configuration data to be downloaded from the external memory device into the first store, while maintaining the functionality of the device. This allows the device to be used to provide two different functionalities, and to be switched between these two functionalities with minimal delay for reconfiguration of the device.

James Tyson

Papers

Bus architecture for system on a chip

Functional pre-configuration of a programmable logic device

Memory access system

Efficient data recovery algorithm for serial data

Updating configuration for programmable logic device