A high-frequency wireless communication system on a single ultrathin silicon on sapphire chip is presented. This system incorporates analog, digital (logic and memory) and high radio frequency circuits on a single ultrathin silicon on sapphire chip. The devices are fabricated using conventional bulk silicon CMOS processing techniques. Advantages include single chip architecture, superior high frequency performance, low power consumption and cost effective fabrication.

High-frequency wireless communication system on a single ultrathin silicon on sapphire chip

A process is disclosed for preparing a silicon-on-sapphire wafer suited for fabrication of fully depleted field effect transistors. A fully depleted field effect transistor (FET) which has minimum parasitic charge in the conduction channel and a process to make same are described. The device is made in and relies on the silicon layer on sapphire which has minimal charge intentionally introduced into the conduction channel. Both N-type and P-type transistors are described. Methods for defining threshold voltage are also described. Specific examples of the devices are presented including specific materials selections for threshold voltage options. Manufacturing processes are described, including a preferred embodiment based on ultra thin silicon on sapphire. The devices can be fabricated using conventional silicon techniques; both silicided and non-silicided versions are presented. Advantages include threshold voltages determined by fundamental material properties; high performance devices due to reduced carrier scattering, low transverse electric fields and elimination of the body effect; threshold voltages virtually independent of temperature; simplicity of modeling due to reduction or elimination of parasitic effects; device and process simplicity; ease of scaling and an option for inherently symmetric threshold voltages for N-channel and P-channel MOSFETs (i.e. .linevert split.V tn .linevert split.=.linevert split.V tp .linevert split.).

Minimum charge FET fabricated on an ultrathin silicon on sapphire wafer

The present invention is generally related to controllably modifying or tailoring the structure of crystalline films to adjust and enhance the material properties of the film, such as optical, mechanical and electrical properties. Crystalline films generally refer to microcrystalline (μc) film, nanocrystalline (nc) film, polycrystalline (poly-c) film, and other crystallized films. The present invention provides a method for controllably obtaining desired grain sizes (or crystal sizes) in crystalline films and for controllably providing a predominance of grains sizes in a predetermined range to adjust and enhance the optical absorption properties of the crystalline film. The present invention also provide a method for controlling the mechanical properties, e.g., stress formation levels, during crystallization of at least a portion of the precursor film. Through control of the stress formation levels, it is possible to controllably adjust and enhance the electrical properties (e.g., doping efficiencies, carrier mobility, Fermi level and minority carrier lifetimes) of the crystallized portion.

Nanostructure tailoring of material properties using controlled crystallization

An integrated circuit comprising an insulating substrate; a layer of silicon formed on said insulating substrate; a p-channel transistor and an n-channel transistor formed in said silicon layer and interconnected in a CMOS circuit; wherein the ratio of transistor p-channel length to transistor n-channel length in the CMOS circuit is less than or equal to one.

Cmos circuitry with shortened p-channel length on ultrathin silicon on insulator

Disclosed is a method of fabricating a semiconductor on insulator composite substrate comprised of a semiconductor layer adjacent an insulator substrate, the defect density profile of the semiconductor layer being low and relatively uniform, a relatively thin region of the semiconductor layer at the semiconductor/insulator interface having a substantially greater defect density The method comprises the steps of depositing the semiconductor layer adjacent the insulator substrate, amorphizing a buried portion of the semiconductor layer without damaging the insulator substrate such as to release contaminants into the semiconductor layer, recrystallizing the amorphous portion of the semiconductor or layer, removing a portion of the semiconductor layer so as to expose the recrystallized layer, and depositing an additional semiconductor layer on the recrystallized layer to provide an essentially defect free semiconductor layer of any desired thickness The provision of semiconductor layers formed by either appropriately selecting the depth within the semiconductor layer at which the amorphization occurs and the width of the amorphized region or permitting self-annealing to occur during the amorphization, or both, having a desired high defect density and interposed between the recrystallized layer and the insulator substrate are also disclosed

Solid phase epitaxy and regrowth process with controlled defect density profiling for heteroepitaxial semiconductor on insulator composite substrates.

A method is provided for producing a low-defect layer of silicon on a sapphire substrate. A silicon-on-sapphire (SOS) wafer is formed by initially epitaxially depositing silicon on the sapphire substrate to form a monocrystalline layer which is substantially free of lattice defects near its surface, but which exhibits a high defect density near the sapphire substrate. The wafer is subsequently subjected to an ion implantation to form an amorphous region in the silicon near the silicon-sapphire interface. The implanted ions are preferably "channeled" through the silicon layer to insure that the amorphous region will be localized in the imperfect region near the substrate, leaving the upper region of the silicon layer undamaged. During a subsequent high temperature anneal cycle, monocrystalline silicon is regrown from the residual upper regions of the silicon down to the silicon-sapphire interface, producing a silicon layer having a greatly reduced defect density throughout the layer.

James W. Mayer

Papers

Method for producing a low defect layer of silicon-on-sapphire wafer