Showing papers by "Jan Craninckx published in 1993"
09 May 1993
TL;DR: A novel high-speed, single-clock-phase current latch has been developed and is combined with a decoder and error correcting circuit in true single clock phase logic, which allows sampling frequencies up to 100 MHz.
Abstract: A 100-MHz 8 bit A/D (analog-to-digital) converter realized in a standard 1.5 /spl mu/m CMOS technology is presented. By implementing a current interpolating technique, the input capacitance has been reduced compared to that of flash converter. As this current interpolating circuit is an analog preprocessing circuit, the speed is mainly determined by the comparators and the digital decoding logic. A novel high-speed, single-clock-phase current latch has been developed. The latch is combined with a decoder and error correcting circuit in true single clock phase logic, which allows sampling frequencies up to 100 MHz.
44 citations