Present industry practice has created a high demand for systems designers with knowledge and experience in using programmable logic in the form of CPLDs and FPGAs in addition to hardware description languages. Many universities offer this type of training in advanced digital engineering courses. This paper describes our experience in integrating VHDL and programmable logic devices based on Xilinx Foundation tools and Altera into a first course in logic design. In the main, student reaction to the course was positive. The course seems to have the right blend of being current (using VHDL and FPGAs) and being hands-on (using bread-boarding). We conclude by stating that in our experience, modeling using VHDL and mapping designs to FPGAs can be effectively integrated into a first course in logic design.

A first course in digital design using VHDL and programmable logic

A distributed processing system includes a plurality of task nodes each configured to have a capability of processing a task using a reconfigurable processor, and having a capability of processing the task using a non-reconfigurable processor if the task is not processed using the reconfigurable processor, and a scheduler node configured to select a task node that is to process the task from the plurality of task nodes.

Distributed processing system, scheduler node and scheduling method of distributed processing system, and program generation apparatus thereof

Genomic data are growing exponentially and are daily scanned by thousands of biologists. To reduce the scan time, efficient parallelism can be exploited by dispatching data among a cluster of processing units able to scan locally and independently their own data. If PC clusters are well suited to support this type of parallelism, we propose to substitute PCs by re-configurable hardware closely connected to a hard disk. We show that low cost FPGA nodes interconnected through a standard Ethernet network may advantageously compete against high performance clusters. A prototype of 48 re-configurable processing nodes has been experimented on two genomic applications: a content-based similarity search and a pattern search.

Cluster of re-configurable nodes for scanning large genomic banks

In this paper, we present an automated flow geared toward the synthesis of application specific micro-controllers for FPGAs, targeted at control dominated applications. Our flow takes as input an application described in C, and uses profiling information to extract a specialized instruction set. This instruction set is then mapped to a generic RISC micro-architecture model, for which we generate a synthesizable VHDL description, along with its associated program. The flow has been validated on a set of representative applications and our preliminary experimental results show that our generated architectures are very competitive with FPGA vendor specific processor soft-cores, in terms of code size, resource usage and performance.

Generating efficient custom FPGA soft-cores for control-dominated applications

Arguably, each computer engineer undergrad should build a simple processor in the pursuit of their degree to help them internalize the basic design principles and properties of a computer. With the proliferation of FPGAs in universities this is, easily, realizable in most undergraduate curricula. Many modern courses on computer architecture or organization rely on MIPS architectures (among others) as the base processor to learn with, but the MIPS architecture has little commercial success and real-world implementations that will allow students to get additional career benefit from building and learning about a used architecture. The increasing industrial interest of RISCV ISA, its free availability, and its early success in real-world adoption makes this processor a great potential candidate in this educational space. This work provides suggestions on how undergraduates should build a RISC-V architecture on an FPGA, and a basic framework of tools and design principles for this exercise.

Framework and Tools for Undergraduates Designing RISC-V Processors on an FPGA in Computer Architecture Education

Field programmable gate arrays are an ideal substrate for computer architecture project courses. FPGA-based processor development offers some learning opportunities that pure simulation approaches cannot rival. This paper first introduces the XSOC Project, a free kit that includes the xr16 RISC CPU core, system-on-a-chip infrastructure, peripheral cores, C compiler, and simulator. Such kits have numerous applications in a first architecture course. It then suggests that FPGA-based processors can also be applied to the study of advanced architecture topics including memory systems, multithreading, LIWs, chip multiprocessors, and architectural support for programming languages and networking.

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Jan Gray

Papers

Hands-on computer architecture: teaching processor and integrated systems design with FPGAs