Instruction-level parallelism (ILP) is a family of processor and compiler design techniques that speed up execution by causing individual machine operations to execute in parallel. Although ILP has appeared in the highest performance uniprocessors for the past 30 years, the 1980s saw it become a much more significant force in computer design. Several systems were built and sold commercially, which pushed ILP far beyond where it had been before, both in terms of the amount of ILP offered and in the central role ILP played in the design of the system. By the end of the decade, advanced microprocessor design at all major CPU manufacturers had incorporated ILP, and new techniques for ILP had become a popular topic at academic conferences. This article provides an overview and historical perspective of the field of ILP and its development over the past three decades.

Instruction-level parallel processing: history, overview, and perspective

In this work we describe a diagnostic fault simulator for sequential circuits which evaluates the effectiveness of a given test set in distinguishing between faults. Diagnostic fault simulation is performed on several ISCAS89 sequential benchmark circuits using two diferent deterministic test sets for each circuit. Several diagnostic measures are reported, including the diagnostic resolution, the diagnostic power, and the sizes of the indistinguishable fault classes. In addition, lists of indistinguishable faults are generated. Use of the diagnostic fault simulator to diagnose faults, given the output responses of failing devices, is also described.

Diagnostic Fault Simulation of Sequential Circuits

The use of the reservation table technique to create optimal cyclic schedules is explored. A detailed discussion and analyses are presented of the properties that determine the theoretical maximum initiation rate, the set of all possible initiation strategies, efficient strategies that yield the maximum realizable performance, and the methods for adding delay to a reservation table so that its maximum realizable rate achieves the theoretical maximum rate. These methods inherently allow multiple devices to be reserved concurrently. They can deal with transport time explicitly. They achieve higher initiation rates by including cycles that involve multiple job initiations. The optimizations are fully valid, not heuristic. These scheduling algorithms can be coupled with the planning environment reported by J.K. Chaar and R.A. Volz (1989). The integrated planning/scheduling framework forms a major component of a software engineering environment that the authors are currently developing. >

Cyclic job shop scheduling using reservation tables

Fault simulators are used extensively in the design of electronic circuits for both testing and fault diagnosis. Complex component types can be easily handled in a fault simulator, since processing occurs in the forward direction only, and various fault models can be accommodated. This research is targeted toward exploiting fault simulation for test generation, design for testability, and fault diagnosis. An existing sequential circuit fault simulator is used, and extensions to the fault simulator for these application areas are described. A nonscan observability enhancement approach is presented, which uses the fault simulator to select a minimal set of probe points for detection of faults previously found to be untestable due to observability problems. The probe points are compressed to a single output pin using an exclusive-OR (XOR) tree. This method can be combined with nonscan controllability enhancement techniques to provide high fault coverages without aaecting the ability to do at-speed testing. The fault simulator is also extended to provide information about the diagnostic capability of a test set and to diagnose failing devices, given the actual output responses. A new diagnostic measure is introduced for sequential circuits starting from an uninitialized state, and algorithms to compute various diagnostic measures are described. Next, simulation-based test generation is explored as an alternative to deterministic approaches. A genetic algorithm (GA) framework is interfaced to the fault simulator to generate test sets with high fault coverages. The GA generates populations of candidate test vectors or test sequences, and the fault simulator is used to evaluate the tness of each test. Various GA parameters are studied, and methods to achieve low execution times are discussed. Generation of test sets for full scan and partial scan circuits which limit the scan operations are also described. Test application time for scan circuits can be iii long, but reductions can be made if ip-op values are not scanned in and out before and after every test vector is applied. Scan-initiated and normal test sequences are evolved by the GA, and sequences having the highest ratio of fault coverage to test application time are selected. Finally, the GA framework is combined with a deterministic test generator for sequential circuits. The hybrid test generator uses deterministic algorithms for fault excitation and propagation and a GA for state justiication. Existing deterministic procedures for state justiication are used only if the genetic approach is unsuccessful. This hybrid approach allows for higher fault …

Simulation-Based Techniques for Sequential Circuit Testing

Concurrent or overlapped processing of more than one task is a common technique used in many computer architectures to increase the throughput. A pipeline is one such form consisting of a set of hardware segments which can be operated in an overlapped fashion. The existing and many proposed pipelines assume that a task must flow synchronously, without wait or preemption, from segment to segment for its execution. In this paper we propose a pipeline model in which priority buffers are provided at every segment to control the flow of tasks. Several different priority implementations are analyzed assuming periodic arrivals of tasks. The characteristics studied are, queue size, wait time and throughput. It is shown that the theoretical maximum throughput of a pipeline is attainable with the use of internal buffers. Moreover, it is shown that a substantial degree of freedom in scheduling of tasks is achieved by these methods.

Pipelines with internal buffers

: A pipeline as defined here is a collection of segments of hardware which can operate simultaneously. A task flows synchronously from segment to segment for its execution. Each task follows one of several distinct task flow patterns which are assumed to be fixed and known in advance. It is characteristic of pipelines that a task can be initiated in the pipeline before an earlier initiated task has completed its execution. A problem arises when two or more tasks try to use the same segment at the same time, causing a collision. Such collisions can be avoided by appropriate scheduling of tasks and/or modification of the pipeline; or the collisions can be resolved at the time and place they occur. These alternatives are studied in this work with the objective that the throughput, i.e., average number of tasks processed per unit time, be maximized while providing considerable flexibility in scheduling of tasks. Collision characteristics of task schedules and pipelines are studied. A methodology for inserting fixed delays in a pipeline to achieve desired collision characteristics is presented.

Janak Himatlal Patel

Papers

Improving the throughput of pipelines with delays and buffers