Knowing that some variables are symmetric in a function has numerous applications; in particular, it can help produce better variable orders for Binary Decision Diagrams (BDDs) and related data structures (e.g., Algebraic Decision Diagrams). It has been conjectured that there always exists an optimum order for a BBD wherein symmetric variables are contiguous. We propose a new algorithm for the detection of symmetries, based on dynamic reordering, and we study its interaction with the reordering algorithm itself. We show that combining sifting with an efficient symmetry check for contiguous variables results in the fastest symmetry detection algorithm reported to date and produces better variable orders for many BDDs. The overhead on the sifting algorithm is negligible.

Symmetry detection and dynamic variable ordering of decision diagrams

Decision diagrams (DDs) are the state-of-the-art data structure in VLSI CAD and have been successfully applied in many other fields. DDs are widely used and are also integrated in commercial tools. This special section comprises six contributed articles on various aspects of the theory and application of DDs. As preparation for these contributions, the present article reviews the basic definitions of binary decision diagrams (BDDs). We provide a brief overview and study theoretical and practical aspects. Basic properties of BDDs are discussed and manipulation algorithms are described. Extensions of BDDs are investigated and by this we give a deeper insight into the basic data structure. Finally we outline several applications of BDDs and their extensions and suggest a number of articles and books for those who wish to pursue the topic in more depth.

Binary decision diagrams in theory and practice

Integrated circuits (ICs) are now designed and fabricated in a globalized multivendor environment making them vulnerable to malicious design changes, the insertion of hardware Trojans/malware, and intellectual property (IP) theft. Algorithmic reverse engineering of digital circuits can mitigate these concerns by enabling analysts to detect malicious hardware, verify the integrity of ICs, and detect IP violations. In this paper, we present a set of algorithms for the reverse engineering of digital circuits starting from an unstructured netlist and resulting in a high-level netlist with components such as register files, counters, adders, and subtractors. Our techniques require no manual intervention and experiments show that they determine the functionality of ${>}{45\%}$ and up to 93% of the gates in each of the test circuits that we examine. We also demonstrate that our algorithms are scalable to real designs by experimenting with a very large, highly-optimized system-on-chip (SOC) design with over 375000 combinational elements. Our inference algorithms cover 68% of the gates in this SOC. We also demonstrate that our algorithms are effective in aiding a human analyst to detect hardware Trojans in an unstructured netlist.

Reverse Engineering Digital Circuits Using Structural and Functional Analyses

Preface. Contributing Authors. Introduction R. Drechsler. 1. Formal Verification. 2. Challenges. 3. Contributions to this Book. 1: What SAT-Solvers Can and Cannot Do E. Goldberg. 1. Introduction. 2. Hard Equivalence Checking CNF Formulas. 3. Stable Sets of Points. 2: Advancements in Mixed BDD and SAT Techniques G. Cabodi, S. Quer. 1. Introduction. 2. Background. 3. Comparing SAT and BDD Approaches: Are they Different? 4. Decision Diagrams as a Slave Engine in General SAT: Clause Compression by Means of ZBDDs. 5. Decision Diagram Preprocessing and Circuit-Based SAT. 6. Using SAT in Symbolic Reachability Analysis. 7. Conclusion, Remarks and Future Works. 3: Equivalence Checking of Arithmetic Circuits D. Stoffel, E. Karibaev, I. Kufareva, W. Kunz. 1. Introduction. 2. Verification Using Functional Properties. 3. Bit-Level Decision Diagrams. 4. Word-Level Decision Diagrams. 5. Arithmetic Bit-Level Verification. 6. Conclusion. 7. Future Perspectives. 4: Application of Property Checking R. Brinkmann, P. Johannsen, K. Winkelmann. 1. Circuit Verification Environment: User's View. 2. Circuit Verification Environment: Underlying Techniques. 3. Exploiting Symmetries. 4. Automated Data Path Scaling to Speed Up Property Checking. 5. Property Checking Use Cases. 6. Summary. 5: Assertion-Based Verification C.N. Coelho Jr, H.D. Foster. 1. Introduction. 2. Assertion Specification. 3. Assertion Libraries. 4. Assertion Simulation. 5. Assertions and Formal Verification. 6. Assertions and Synthesis. 7. PCI Property Specification Example. 8. Summary. 6: Formal Verification for Nonlinear Analog Systems W. Hartong, R. Klausen, L. Hedrich. 1. Introduction. 2. System Description. 3. Equivalence Checking. 4. Model Checking. 5. Summary. 6. Acknowledgement. Appendix: Mathematical Symbols. Index.

Advanced Formal Verification

This paper proposes a new approach to multi-level logic optimization based on ATPG (Automatic Test Pattern Generation). Previous ATPG-based methods for logic minimization suffered from the limitation that they were quite restricted in the set of possible circuit transformations. We show that the ATPG-based method presented here allows (in principle) the transformation of a given combinational network C into an arbitrary, structurally different but functionally equivalent combinational network C'. Furthermore, powerful heuristics are presented in order to decide what network manipulations are promising for minimizing the circuit. By identifying indirect implications between signals in the circuit, transformations can be derived which are “good” candidates for the minimization of the circuit. In particular, it is shown that Recursive Learning can derive “good” Boolean divisors justifying the effort to attempt a Boolean division. For 9 out of 10 ISCAS-85 benchmark circuits our tool HANNIBAL obtains smaller circuits than the well-known synthesis system SIS.

http://www.cecs.uci.edu/~papers/compendium94-03/papers/1994/iccad94/pdffiles/01a_2.pdf

Multi-level logic optimization by implication analysis

Addresses the problem of the detection of symmetries of Boolean functions. To know these symmetries may be important in several stages of logic design, e.g. in logic optimization, in logic synthesis, and in technology mapping. Reduced ordered binary decision diagrams (ROBDDs) play an important role in these tools. Using this representation form for Boolean functions there is a simple symmetry test by checking if certain cofactor functions are equivalent, i.e. if their ROBDD representations are the same. Unfortunately, this procedure may be very time and storage consuming because of the necessary cofactor computations. The approach presented in this paper uses preprocessing methods to find as many asymmetric pairs of variables as possible to avoid cofactor computations at the end. For that, special properties of the ROBDD structure as well as properties of Boolean functions are used. Experimental results on a large number of benchmarks show that this is a very efficient approach.

Detection of symmetry of Boolean functions represented by ROBDDs

This paper addresses problems that arise while checking the equivalence of two Boolean functions under arbitrary input permutations The permutation problem has several applications in the synthesis and verification of combinational logic: it arises in the technology mapping stage of logic synthesis and in logic verification A popular method to solve it is to compute a signature for each variable that helps to establish a correspondence between the variables Several researchers have suggested a wide range of signatures that have been used for this purpose However, for each choice of signature, there remain variables that cannot be uniquely identified Our research has shown that, for a given example, this set of problematic variables tends to be the same-regardless of the choice of signatures The paper investigates this problem

http://cs.ecs.baylor.edu/~maurer/CSI5346/LimSigs.pdf

Limits of using signatures for permutation independent Boolean comparison

Permutation and phase independent Boolean comparison

The problem of checking the equivalence of two Boolean functions under arbitrary input permutations and/or input plane assignments is considered. This problem has several applications in the synthesis and verification of combinational logic. The approach presented computes a signature for each variable or phase of a variable that will help establish correspondence of variables or phases of variables. The strength of the proposed approach depends on the ability to quickly derive a signature with minimum aliasing. Aliasing refers to two different variables or phases having the same signature, thus rendering this signature useless for the purpose of distinguishing between them. Experimental results on a large number of examples establish the efficacy of this approach. >

With the chip complexity constantly increasing, the difficulty as well as the importance of functional verification of new product designs has been increased. It is not only more important to get error-free designs. Moreover, it becomes an increasingly difficult task for a team of human designers to carry out a full design without errors. The traditional training of new verification engineers has to be adapted to the new situation. New skills are necessary. For these reasons, nearly all major universities offer lectures on basic verification techniques such as propositional temporal logic, model checking, equivalence checking, and simulation coverage measures. The present book is designed as a textbook covering one of the most important aspects in the verification process e equivalence checking of Boolean circuits. Equivalence Checking of Digital Circuits is a textbook for advanced students in electrical and computer engineering, but is also intended for researchers who will find it useful as a reference text.

Janett Mohnke

Papers

Detection of symmetry of Boolean functions represented by ROBDDs

Limits of using signatures for permutation independent Boolean comparison

Permutation and phase independent Boolean comparison

Permutation and phase independent Boolean comparison

Equivalence Checking of Digital Circuits: Fundamentals, Principles, Methods