Integration 

TL;DR: This survey describes research directions in netlist partitioning during the past two decades in terms of both problem formulations and solution approaches, and discusses methods which combine clustering with existing algorithms (e.g., two-phase partitioning).

TL;DR: The state of the art in networks on chip is reviewed, an infrastructure called Hermes is described, targeted to implement packet-switching mesh and related interconnection architectures and topologies and the design validation of the Hermes switch is presented.

TL;DR: A comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for high-performance V LSI circuit design under the deep submicron fabrication technologies.

TL;DR: This review eases the choice of a decent exploration policy by providing a comprehensive survey and classification of recent related work focused on system-on-a-chip designs, particularly those used for network processors.

TL;DR: This work curve fit second and third-order polynomials to circuit delay, energy, and power dissipation results based on HSpice simulations utilizing the Predictive Technology Model (PTM) and International Technology Roadmap for Semiconductors (ITRS) models.