There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

Experience and Educationis the best concise statement on education ever published by John Dewey, the man acknowledged to be the pre-eminent educational theorist of the twentieth century. Written more than two decades after Democracy and Education(Dewey's most comprehensive statement of his position in educational philosophy), this book demonstrates how Dewey reformulated his ideas as a result of his intervening experience with the progressive schools and in the light of the criticisms his theories had received. Analysing both "traditional" and "progressive" education, Dr. Dewey here insists that neither the old nor the new education is adequate and that each is miseducative because neither of them applies the principles of a carefully developed philosophy of experience. Many pages of this volume illustrate Dr. Dewey's ideas for a philosophy of experience and its relation to education. He particularly urges that all teachers and educators looking for a new movement in education should think in terms of the deeped and larger issues of education rather than in terms of some divisive "ism" about education, even such an "ism" as "progressivism." His philosophy, here expressed in its most essential, most readable form, predicates an American educational system that respects all sources of experience, on that offers a true learning situation that is both historical and social, both orderly and dynamic.

经验与教育 = Experience and education

The scaling of microchip technologies has enabled large scale systems-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the implementation of scalable communication structures. This survey presents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. First, research relating to the actual network design is reviewed. Then system level design and modeling are discussed. We also evaluate performance analysis techniques. The research shows that NoC constitutes a unification of current trends of intrachip communication rather than an explicit new alternative.

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A survey of research and practices of Network-on-chip

コンピュータ・サイエンス : ACM computing surveys

by J. Biggs and C. Tang, Maidenhead, England,
Open University Press, 2007, 360 pp., £29.99, ISBN-13: 978-0-335-22126-4

Teaching for quality learning at university

The issues of applying the code-division multiple access (CDMA) technique to an on-chip packet switched communication network are discussed in this paper. A packet switched network-on-chip (NoC) that applies the CDMA technique is realized in register-transfer level (RTL) using VHDL. The realized CDMA NoC supports the globally-asynchronous locally-synchronous (GALS) communication scheme by applying both synchronous and asynchronous designs. In a packet switched NoC, which applies a point-to-point connection scheme, e.g., a ring topology NoC, data transfer latency varies largely if the packets are transferred to different destinations or to the same destination through different routes in the network. The CDMA NoC can eliminate the data transfer latency variations by sharing the data communication media among multiple users concurrently. A six-node GALS CDMA on-chip network is modeled and simulated. The characteristics of the CDMA NoC are examined by comparing them with the characteristics of an on-chip bidirectional ring topology network. The simulation results reveal that the data transfer latency in the CDMA NoC is a constant value for a certain length of packet and is equivalent to the best case data transfer latency in the bidirectional ring network when data path width is set to 32 bits.

Applying CDMA Technique to Network-on-Chip

In Interconnect-centric Design for Advanced SoC and NoC, we have tried to create a comprehensive understanding about on-chip interconnect characteristics, design methodologies, layered views on different abstraction levels and finally about applying the interconnect-centric design in system-on-chip design. Traditionally, on-chip communication design has been done using rather ad-hoc and informal approaches that fail to meet some of the challenges posed by next-generation SOC designs, such as performance and throughput, power and energy, reliability, predictability, synchronization, and management of concurrency. To address these challenges, it is critical to take a global view of the communication problem, and decompose it along lines that make it more tractable. We believe that a layered approach similar to that defined by the communication networks community should also be used for on-chip communication design. The design issues are handled on physical and circuit layer, logic and architecture layer, and from system design methodology and tools point of view. Formal communication modeling and refinement is used to bridge the communication layers, and network-centric modeling of multiprocessor on-chip networks and socket-based design will serve the development of platforms for SoC and NoC integration. Interconnect-centric Design for Advanced SoC and NoC is concluded by two application examples: interconnect and memory organization in SoCs for advanced set-top boxes and TV, and a case study in NoC platform design for more generic applications.

Interconnect-Centric Design for Advanced SOC and NOC

Compared to the well understood macro networks, networks-on-chip introduce novel design challenges. The characteristics of the system data flows and the knowledge of the required wire lengths can be exploited to optimize for speed and power consumption. A component library for flexible construction of interconnection architectures is being developed at the Tampere University of Technology to enable the creation of application development platforms. The overall design flow of these development platforms is reviewed in this paper. Network-on-chip topology optimization is addressed by describing the methodologies used by an effective design automation tool. The detailed cost functions of the tool capture the factors contributing to the speed and power consumption of asynchronous interconnections, while different abstraction level input information is supported. A case study into the application domain of industrial process control and monitoring is presented in order to evaluate the result quality.

Topology optimization for application-specific networks-on-chip

An interconnect IP (intellectual Property) node architecture for flexible on-chip communication is introduced. This architecture is targeted for communication in future gigatransistor SoC (System-on-Chip) designs. The interconnect IP will be used as a testing platform when the efficiency of network topologies and routing schemes are investigated for the on-chip environment. The interconnect node uses packet based communication and forms a reusable component itself. The node is constructed from a collection of parameterized and reusable hardware blocks, which include components such as FIFO buffers, routing controllers and standardized interface wrappers. A node can be tuned to fulfill the desired characteristics of communication by selecting the internal architecture properly.

Interconnect IP node for future system-on-chip designs

Processor Design addresses the design of different types of embedded, firmware-programmable computation engines. Because the design and customization of embedded processors has become a mainstream task in the development of complex SoCs (Systems-on-Chip), ASIC and SoC designers must master the integration and development of processor hardware as an integral part of their job. Even contemporary FPGA devices can now accommodate several programmable processors. There are many different kinds of embedded processor cores available, suiting different kinds of tasks and applications. Processor Design provides insight into a number of different flavors of processor architectures and their design, software tool generation, implementation, and verification. After a brief introduction to processor architectures and how processor designers have sometimes failed to deliver what was expected, the authors introduce a generic flow for embedded on-chip processor design and start to explore the vast design space of on-chip processing. The types of processor cores covered include general purpose RISC cores, traditional DSP, a VLIW approach to signal processing, processor cores that can be customized for specific applications, reconfigurable processors, protocol processors, Java engines, and stream processors. Co-processor and multi-core design approaches that deliver application-specific performance over and above that which is available from single-core designs are also described. The special design requirements for processors targeted for FPGA implementation, clock generation and distribution in microprocessor circuits, and clockless realization of processors are addressed. Tools and methodologies for application-specific embedded processor design are covered, together with processor modelling and early estimation techniques, and programming tool support for custom processors. The book concludes with a glance to the future of embedded on-chip processors.

Jari Nurmi

Papers

Applying CDMA Technique to Network-on-Chip

Interconnect-Centric Design for Advanced SOC and NOC

Topology optimization for application-specific networks-on-chip

Interconnect IP node for future system-on-chip designs

Processor Design: System-On-Chip Computing for ASICs and FPGAs