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Showing papers by "Javed I. Khan published in 2022"


Journal ArticleDOI
TL;DR: This paper presents CLB, a programmable switch-based general-purpose in-network load balancer that can adapt to traffic changes at a very high speed and leads to performance improvement compared to other load balancing schemes.
Abstract: This paper presents CLB, a programmable switch-based general-purpose in-network load balancer that can adapt to traffic changes at a very high speed. It uses Weighted-Cost Multipath (WCMP) mechanism for traffic-aware load balancing over many paths at a coarse-grained precision. CLB can be configured to match the load balancing requirements of a wide range of applications at line rate. We have analytically shown that CLB can achieve a bounded response time to traffic changes in the data plane. We implement CLB using the P4 programming language. Our experimental evaluation shows CLB can successfully distribute the incoming load over multiple paths for a given path-weight distribution and leads to performance improvement compared to other load balancing schemes.

14 citations


Journal ArticleDOI
TL;DR: In this paper , the effect of different process parameters on the growth rate and desulfurization capability of the bacterial consortium IQMJ-5 have been examined, including temperature of incubation, initial pH of the medium, and DBT concentration.
Abstract: Biodesulfurization is a promising approach, capable of reducing the sulfur content of recalcitrant sulfur-containing heterocyclic compounds such as dibenzothiophene and their alkylated derivatives. The performance of bio-desulfurization is undoubtfully dependent on different operating parameters. The effect of different process parameters on the growth rate and desulfurization capability of the bacterial consortium IQMJ-5 have been examined. The parameters that were optimized include the temperature of incubation, initial pH of the medium, and DBT concentration. In addition, the effect of several carbon and sulfur compounds on the growth of bacterial consortia IQMJ-5 was also analyzed. Moreover, the concentration of the most effective carbon compound was also examined in shake flask fermentation. The results showed that 25 º C temperature, 7.6 pH, and 0.3 mM DBT were the optimum conditions for the highest growth and desulfurization of the DBT. In addition, glycerol and Na 2 SO 4 were the bioavailable carbon and sulfur sources respectively, at which the consortium IQMJ-5 showed maximum growth. Moreover, 2gL -1 glycerol appeared as the carbon concentration at which the consortium IQMJ-5 showed the highest activity. An enhanced rate of desulfurization was encountered when a medium with optimized conditions was employed, compared to non-optimized conditions. The current research study uncovered the potential of the bacterial consortium IQMJ-5 to desulfurize sulfur-containing organic compounds at the optimized conditions of different process parameters.

5 citations


Journal ArticleDOI
01 Jul 2022
TL;DR: This work presents P4TE, an in-band traffic monitoring, load-aware packet forwarding, and flow rate controlling mechanism for traffic engineering in fat-tree topology-based data center networks using PISA switches that achieves sub-RTT reaction time to change in network conditions, improved flow completion time, and balanced link utilization.
Abstract: This work presents P4TE, an in-band traffic monitoring, load-aware packet forwarding, and flow rate controlling mechanism for traffic engineering in fat-tree topology-based data center networks using PISA switches. It achieves sub-RTT reaction time to change in network conditions, improved flow completion time, and balanced link utilization. Unlike the classical probe-based monitoring approach, P4TE uses an in-band monitoring approach to identify traffic events in the data plane. Based on these events, it re-adjusts the priorities of the paths. It uses a heuristic-based load-aware forwarding path selection mechanism to respond to changing network conditions and control the flow rate by sending feedback to the end hosts. It is implementable on emerging v1model.p4 architecture-based programmable switches and capable of maintaining the line-rate performance. Our evaluation shows that P4TE uses a small amount of resources in the PISA pipeline and achieves an improved flow completion time than ECMP and HULA.

4 citations


Journal ArticleDOI
TL;DR: This work presents an open-source P4 16 compiler backend for the V1Model architecture-based programmable switches that uses heuristic-based mapping algorithms to map a P 4 16 program over the hardware resources of a V1 model switch.
Abstract: The P4 language has become the dominant choice for programming the reconfigurable match-action table based programmable switches. V1Model architecture is the most widely available re-alization of this paradigm. The open-source compiler frontend developed by the P4 consortium can execute syntax analysis and derive a hardware-independent representation of a program written using the latest version of P4 (also known as P4 16 ). A compiler backend is required to map this intermediate representation to the hardware resources of a V1Model switch. However, there is no open-source compiler backend available to check the realizability of a P4 16 program over a V1Model switch. Proprietary tools provided by different hardware vendors are available for this purpose. However, they are closed source and do not provide access to the internal mapping mechanisms. Which inhibits experimenting with new mapping algorithms and innovative instruction sets for reconfigurable match-action table architecture. Moreover, the proprietary compiler backends are costly and come with various non-disclosure agreements. These factors pose serious challenges to programmable switch-related research. In this work, we present an open-source P4 16 compiler backend for the V1Model architecture-based programmable switches. It uses heuristic-based mapping algorithms to map a P4 16 program over the hardware resources of a V1Model switch. It allows developers to rapidly prototype different mapping algorithms. It also gives various resource usage statistics of a P4 16 program, enabling comparison among multiple P4 16 schemes.

1 citations


Proceedings ArticleDOI
21 Nov 2022
TL;DR: In this paper , an open-source compiler backend for compiling P416 targeted for the V1Model architecture-based programmable switches is presented. But the compiler is not fully open source and does not provide access to the internal mapping mechanisms.
Abstract: Very few of the innovations in deep networking have seen data center scale implementation. Because, the Data Center network’s extreme scale performance requires hardware implementation, which is only accessible to a few. However, the emergence of reconfigurable match-action table (RMT) paradigm-based switches have finally opened up the development life cycle of data plane devices. The P4 language is the dominant language choice for programming these devices. Now, Network operators can implement the desired feature over white box RMT switches. The process involves an innovator writing new algorithms in the P4 language and getting them compiled for the target hardware. However, there is still a roadblock. After designing an algorithm, the P4 program’s compilation technology is not fully open-source. Thus, it is very difficult for an average researcher to get deep insight into the performance of his/her innovation when executed at the silicon level. There is no open-source compiler backend available for this purpose. Proprietary compiler backends provided by different hardware vendors are available for this purpose. However, they are closed-source and do not provide access to the internal mapping mechanisms. Which inhibits experimenting with new mapping algorithms and innovative instruction sets for reconfigurable match-action table architecture. This paper describes our work toward an open-source compiler backend for compiling P416 targeted for the V1Model architecture-based programmable switches..