An emulation device including a serial scan testability interface having at least first and second scan paths, and state machine circuitry connected and responsive to said second scan path generally operable for emulation control of logical circuitry associated with said emulation device.

Emulation devices, systems and methods utilizing state machines

A data processing device including a semiconductor chip, an electronic processor on-chip and an on-chip condition sensor connected to the electronic processor for analysis of the operations.

Processor condition sensing circuits, systems and methods

A data processor (3) executes a real time trace function which allows an external development system (7) to dynamically observe internal operations of data processor (3) without assuming a type or availability of an external bus and without significantly impacting the efficiency and speed of the data processor (3). A debug module (10) of data processor (3) provides a parallel output port for providing internal operating information via a DDATA signal and a PST signal. The DDATA signal provides data which reflects operand values and the PST signal provides encoded status information which reflects an execution status of a central processing unit 92). Furthermore, the DDATA signal also provides captured instruction address program flow changes to allow external development system (7) to trace an exact program flow without requiring an externally visible address bus or an externally visible data bus.

Data processing system for performing a debug function and method therefor

An in-circuit emulator (ICE) for hardware/software development and debugging microprocessors. Program execution reconstruction is extracted from an on-board cache memory. An external ICE enclosure interfaces to a target system microprocessor via a cable and a buffer/interface pod. A control program directs a non-intrusive emulation and a monitor program resides in a personal computer host and supports ICE commands. The monitor program allows a user to follow a target system's program flow, to capture related processor information, to make program modifications, and allows the user to restart programs. An on-line disassembler presents a display so as to allow the designer to examine memory, using instruction mnemonics rather than hexadecimal values, thus improving the designer's ability to read program memory. A bit trace buffer records the state of each the microprocessor's signals during each cycle of each instruction. Multiple breakpoints allow a system developer to control a program in ROM, as well as one resident in RAM. An external-range hardware breakpoint and up to sixteen software breakpoints are provided and these allow a designer to display, set and reset breakpoint addresses.

High speed microcomputer in-circuit emulator

A microprocessor is disclosed herein having an external command mode for directly accessing the execution unit, responsive to externally generated commands and instructions. An external instruction path is provided, as well as a conventional processor-driven instruction path. A multiplexer is provided that selects which of the instruction paths is actually supplied to the execution unit. Using the external command mode, the user can examine and modify registers, memory, and I/O space without otherwise affecting their contents. Any instruction executable by the execution unit is executable in the external command mode. Because direct access is provided into the execution unit, there is no implicit updating that would otherwise affect the state of the processor and require saving to an alternate memory. The present invention is implemented with a conventional test access port designed in accordance with the IEEE 1149.1 boundary scan standard, with modification to include an instruction register, a data register, and control logic. The external command mode is applicable to single and multiple pipeline processors. The circuit described herein includes several selectors for selecting between the probe mode and the processor-driven mode of operation, including an external pin, an external command, and a debug exception. For ascertaining if the circuit is in the external command mode, an acknowledge pin is provided to indicate when the execution unit is ready to accept an instruction in the probe model.

Microprocessor with an external command mode for diagnosis and debugging

A data processing system having a debug peripheral is provided. The debug peripheral is coupled to a central processing unit and memory via an internal communications bus. The debug peripheral is a single-word dual port memory with parallel read-write write access on one side, and synchronous, full-duplex serial read-write access on the other side. The serial side of the debug peripheral is connected to external emulation hardware by means of a three-pin synchronous serial interface. The parallel access is via a connection to a core central processing unit (CPU) internal communications bus. The debug peripheral is addressed at sixteen adjacent locations in the CPU memory space. During a debug interlude, the debug peripheral assumes control of the CPU by providing an interrup signal to the CPU, and thereby causing the CPU to fetch instructions directly from the debug peripheral. The debug peripheral receives instructions from the external emulation hardware, and provides the debug instructions to the CPU, in response to an instruction address provided by the CPU.

No-chip debug peripheral which uses externally provided instructions to control a core processing unit

A data processor (11) with development support features includes an alternate mode of operation in which instructions are received by means of an externally-controlled path. The connections used by the externally-controlled path are not shared by any system resources accessible to the data processor (11) in the normal mode of operation, but are used by other development support features in the normal mode. In a preferred embodiment, an integrated circuit microcomputer (10) includes such a data processor (11) as its CPU. The CPU (11) has access to on-chip peripherals and memory, in addition to off-chip peripherals (13,15) and memory (14), in both the normal and alternate modes of operation, by means of a parallel bus (12) which it operates as a bus master. In the alternate mode, the CPU receives instructions by means of a serial bus on which the CPU is a slave device.

Data processor with development support features

A data processor is adapted for operation with a memory containing a plurality of items of operating information for the data processor. In addition a cache stores a selected number of all of the items of the operating information. When the cache provides an item of operating information, the memory is not requested to provide the item so that a user of the data processor cannot detect the request for the item. A disable circuit is provided to prevent the cache from providing the item when a signal external to the data processor is provided. Consequently, a user, with the external signal, can cause the data processor to make all of its requests for items of operating information to the memory where these requests can be detected.

Cache disable for a data processor

The present invention relates in general to a data processing system (10), and more particularly to a method and apparatus for controlling showcycles in a data processing system (10) to provide user control over the tradeoff between internal bus visibility and operating performance. In one embodiment, the functionality of one or more register control bits (100, 102) can be combined with the functionality of one or more externally provided signals (78) to allow the user to have a wide range of control over the show cycles provided on external bus 12. The user is thus able to continuously select and change which information is provided by way of show cycles on external bus 12. As a result, the difficulty of debugging software program code can potentially be reduced.

Method and apparatus for controlling show cycles in a data processing system

A debug peripheral (16) is provided for real-time in-circuit emulation for high speed microcontrollers and microprocessors. The debug perhipheral (16) is a single-word dual-port memory with parallel read-write access on one side, and synchronous, full-duplex serial read-write access on the other side. A shift register (22) in the debug peripheral (16) functions as an instruction memory for a core central processing unit (CPU) (12). Three-­pins (28,30,32) on the debug peripheral (16) provide the serial interface to an external development system, while parallel access is via a normal connection to the CPU internal bus (18). The debug peripheral (16) is addressed at a number of adjacent locations in the CPU (12) memory space. During emulation (debug) mode, the CPU (12) fetches instructions from the debug peripheral (16), rather than the memory (14). Instructions are serially loaded into the shift register (22) from the development system, via the serial interface, and transferred to the CPU via the parallel interface.

Jay A. Hartvigsen

Papers

No-chip debug peripheral which uses externally provided instructions to control a core processing unit

Data processor with development support features

Cache disable for a data processor

Method and apparatus for controlling show cycles in a data processing system

Debug peripheral for microcomputers, microprocessors and core processor integrated circuits and system using the same