J
Jay W. Gustin
Researcher at Honeywell
Publications - 29
Citations - 474
Jay W. Gustin is an academic researcher from Honeywell. The author has contributed to research in topics: Network packet & Controller (computing). The author has an hindex of 9, co-authored 29 publications receiving 474 citations.
Papers
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Patent
Emulator for visual display object files and method of operation thereof
William L. Call,Laurence A. Clawson,Paul S. Connolly,Ronald J. Freimark,Jay W. Gustin,Michael L. Hodge,Paul Mcgaugh,Donald W. Moore,Elliott Rachlin,Steven C. Ramsdell +9 more
TL;DR: In this article, a system for emulating on a non-native computer (305), a native environment for a visual display object file for a real-time process control system (100) and a real time process control systems employing the emulator.
Patent
Method and apparatus for a redundancy approach in a processor based controller design
TL;DR: In this paper, a system for handling data of a process with a primary controller (30) and a redundant controller (40) is described. But the primary processor is not operable to perform other tasks by using a high speed bus.
Patent
Clock synchronizing method over fault-tolerant etherent
TL;DR: In this paper, a packet passing from an Ethernet Media Access Controller (MAC) to a Physical Interface Transceiver (PHY) is detected as a time synchronization packet from the time master.
Proceedings ArticleDOI
An open solution to fault-tolerant Ethernet: design, prototyping, and evaluation
TL;DR: Experimental shows that OFTE performs efficiently, achieving less than 1 ms end to end LAN swapping time and less than 2 sec failover time, and that concurrent application and system loads have little impact on the performance of failure detection and recovery operations.
Patent
Error detection and correction apparatus in a BY-4 RAM Device
David L. Kirk,Jay W. Gustin +1 more
TL;DR: In this paper, an error detection and correction (EDAC) apparatus interfaces with the memory unit for detecting and correcting a single bit error of the computer word, detecting a two bit error, detecting all two, three, and four bit errors of a single memory device.