A zener diode random number generator circuit is described which produces a random binary number output having a statistical distribution exhibiting a controlled degree of randomness determined in response to an input control signal. A microprocessor feedback circuit monitors the random number output and produces the input control signal in response to the difference between the degree of randomness of the output signal and that of a pre-determined statistical distribution. The digital feedback automatically adjusts the zener diode biasing point and the limiter threshold such that part-to-part tolerance, component aging, temperature variations, or voltage fluctuations will not adversely affect the randomness of the bit stream output. In the preferred embodiment, the microprocessor tests the ratio of ONES bits to ZERO bits of the random number such that a desired 1:1 ONES/ZERO ratio is approximated.

Random number generator with digital feedback

An RNG circuit is connected to the parallel port of a computer. The circuit includes a flat source of white noise and a CMOS amplifier circuit compensated in the high frequency range. A low-frequency cut-off is selected to maintain high band-width yet eliminate the 1/f amplifier noise tail. A CMOS comparator with a 10 nanosecond rise time converts the analog signal to a binary one. A shift register converts the serial signal to a 4-bit parallel one at a sample rate selected at the knee of the serial dependence curve. Two levels of XOR defect correction produce a BRS at 20 kHZ, which is converted to a 4-bit parallel word, latched and buffered. The entire circuit is powered from the data pins of the parallel port. A device driver interface in the computer operates the RNG. The randomness defects with various levels of correction and sample rates are calculated and the RNG is optimized before manufacture.

Random number generator and generation method

A random number generating apparatus which is suitable for miniaturization and which can easily generate binary random numbers that are cryptographically secure is provided. The apparatus comprises: a semiconductor device having a junction; reverse bias applying circuit for applying a reverse bias voltage of a degree so as to cause a breakdown current in the junction; and a binarizing circuit for binarizing a noise signal created in a current path including said junction for generating random numbers from the binarized signal.

Random number generating apparatus

A hardware random-number generator is provided Random shot noise is generated by first and second quantum random shot-noise generators A differential amplifier is provided in electrical communication with the shot-noise generators to subtract signals produced by the shot-noise generators An analog comparator is provided in electrical communication with the differential amplifier to quantize a difference signal produced by the differential amplifier

Hardware random-number generator

A method and circuit is presented for generating a random bit stream based on thermal noise of a Complementary Metal Oxide Semiconductor (CMOS) device. A circuit implementing the invention preferably includes at least a pair of identically implemented thermal noise generators whose outputs feed a differential amplifier. The differential amplifier measures and amplifies the difference between the noise signals. A sampling circuit compares the difference with a threshold value that is selected to track with process/voltage/temperature variations of the noise generator circuits to output a binary bit having a bit value determined according to the polarity of the noise difference signal relative to the threshold value. The sampling circuit may be clocked to generate a random bit stream.

Random bit stream generation by amplification of thermal noise in a CMOS process

The present invention relates to a binary random noise generator for the stochastic coding of digital or analog information, comprising a comparator having two inputs, one of which receives a reference voltage and the other a random analog noise coming from a source of noise, said comparator supplying at its output a binary signal with random transitions, said generator comprising a clock and a logic system which, on the one hand, effect the sampling of the binary signal with random transitions in synchonism with the frequency of said clock and, on the other hand, ensure the strict equiprobality of the two logic states of said binary signal with random transitions, without increasing the radius of correlation. The invention is more particularly applied to the stochastic coding of information with a view to calculation or transmission, with equidistribution of binary variable.

Analog noise generator

The performance of a random reference correlator (RRC) in terms of its precision is studied. It is shown that the precision depends almost entirely on a certain "peak factor". Processes with high peak factors must be clipped, which creates a compromise between the resulting bias and the optimization of precision. In this case a clipping factor has been defined. It is shown that, for clipping level values between 1 and 1.5 times the rms value, the distortion is reasonably acceptable and the variance of the estimate is of the same order of magnitude as that of direct estimators. A prototype, built with high-speed TTL logic circuits, allows incremental delays of 20 ns to be obtained.

Jean-Claude Prof Hoffmann

Papers

Analog noise generator

On the performance of a random reference correlator (Corresp.)