A transceiver for a RFID reader and a transceiver for a RFID transponder (tag) allow communication between the two devices. The RFID reader utilizes an analog front end and a digital backend. In the receiver portion of the transceiver, the front end of the RFID reader uses a pair of down-conversion mixers to demodulate a received signal into in-phase (I) and quadrature (Q) components and analog-to-digital converters (ADC) digitize the signal. A digital signal processor (DSP) in the back end processes the digital signal and uses a matched filter for data detection. The RFID tag receives an inductively coupled signal from the reader and the receiver portion of the tag uses a pulse/level detector that employs an analog comparator and a sample and hold circuit to detect the received signal. A digital decoder/controller is used to decode the incoming data and to establish a sampling clock for the pulse/level detector. An automatic gain control (AGC) circuit adjusts a receiver gain according to the received signal strength and controls tuning of magnetic coupling circuitry.

Multi-protocol radio frequency identification reader tranceiver

We propose design techniques that enable the realization of power-efficient single-bit CT-ΔΣ ADCs at multi-Gb/s speeds. An FIR DAC [1] is used to reduce sensitivity to clock jitter and relax loop filter linearity. A mostly analog path compensates the modulator for the delay introduced by the FIR DAC. The CTDSM samples at 3.6GS/s, has 83dB DR in 36MHz BW, and occupies 0.12mm2 in 90nm CMOS. Dissipating 15mW from a 1.2V supply, it thereby achieves an FoM SNDR of 72.8fJ/level, which is an improvement over the state of the art for converters with bandwidths greater than 20MHz.

A 15mW 3.6GS/s CT-ΔΣ ADC with 36MHz bandwidth and 83dB DR in 90nm CMOS

This paper presents a continuous-time ΔΣ modulator targeted at optimizing power efficiency for input bandwidth exceeding 50 MHz. Delay in the feedback path is carefully minimized and traditional techniques for DAC mismatch correction and excess loop delay compensation are both replaced with digital schemes. Power is also minimized by relaxing loop filter BW requirements and using a power efficient opamp topology. The modulator achieves 73 dB dynamic range (DR) in 80 MHz BW while consuming 23 mW. The peak SNR is 70 dB and the peak SNDR is 67.5 dB, resulting in FOMs of 168 dB and 163 dB based on DR and SNDR, respectively.

A 23 mW, 73 dB Dynamic Range, 80 MHz BW Continuous-Time Delta-Sigma Modulator in 20 nm CMOS

This paper presents a practical way to achieve both wide signal bandwidth and high dynamic range in a continuous- time (CT) delta-sigma modulator. Quantization noise is suppressed aggressively by increasing the effective order of the noise transfer function based on a sturdy multi-stage noise-shaping (SMASH) architecture. The proposed CT SMASH architecture has a much wider signal bandwidth which was limited in the discrete-time (DT) SMASH architecture due to the inherent sampling frequency limitation of DT implementation. Furthermore, the proposed CT SMASH architecture provides better quantization noise suppression by more completely canceling the quantization noise from the $1{\hbox {st}}$ -loop. The CT SMASH architecture is implemented with several efficient circuit techniques suitable for high operation speed. As a result, the prototype fabricated in 28 nm CMOS achieves DR of 85 dB, peak SNDR of 74.9 dB, SFDR of 89.3 dBc, and Schreier FOM of 172.9 dB over a 50 MHz bandwidth at a 1.8 GHz sampling frequency.

A Continuous-Time Sturdy-MASH $\Delta\Sigma$ Modulator in 28 nm CMOS

A third-order single-loop continuous-time sigma-delta modulator (CTSDM) with 6-bit asynchronous successive approximation register (ASAR) quantizer and digital ΔΣ truncator for WCDMA/GSM/EDGE cellular systems is presented. The proposed ASAR-based quantizer reduces the area and power of the modulator dramatically by utilizing the digital truncation technique. By using the 6-bit ASAR quantizer, the sampling frequency is lowered, which reduces the design efforts not only in system level but also in the modulator. In addition, the ac-coupled push-pull stage is employed to improve the high-frequency driving capability of the first integrator. Sampling at 65 MHz, the modulator achieves 83.4 dB dynamic range (DR) and 80/79.6 dB peak SNR/SNDR with 1.92 MHz bandwidth in WCDMA mode. In GSM/EDGE mode, the DR is 96.2 dB. Fabricated in 40-nm CMOS, the modulator occupies 0.051 mm 2 and consumes 1.91 mW from a 1.2-V supply. A 64fJ/conv.-step figure of merit is achieved.

A 64-fJ/Conv.-Step Continuous-Time $\Sigma \Delta$ Modulator in 40-nm CMOS Using Asynchronous SAR Quantizer and Digital $\Delta \Sigma$ Truncator

A low-power continuous-time ΔΣ ADC for HSDPA (High-Speed Downlink Packet Access) applications provides 83 dB dynamic range and 1.92 MHz bandwidth. A high sample rate (245.76 MHz) and an FIR filter in the outer feedback path minimize susceptibility to jitter. A TIA-based integrator with direct connection of inner feedback DAC current sources to integration capacitors supports the high sample rate. The modulator, implemented using 40 nm CMOS, dissipates only 2.8 mW and achieves a 110 fJ / conversion step figure-of-merit.

A 2.8 mW ΔΣ ADC with 83 dB DR and 1.92 MHz BW using FIR outer feedback and TIA-based integrator

An interpolating sample rate converter that provides rate conversion by a factor of M/N comprising: an upsampler that upsamples an input data stream by a factor of M; a filter that shapes the upsampled data stream in accordance with a predetermined power spectrum; and a downsampler that downsamples the upsampled and shaped signal by a factor of N to produce an output data stream; wherein the upsampler and filter are implemented, at least in part, by a cascaded integrator-comb filter; and wherein the upsampling factor M is a natural number and the downsampling factor N is a rational number but not necessarily a natural number.

Sample rate converter with rational numerator or denominator

In this paper, we present a hybrid operational amplifier (opamp) frequency compensation topology to maximize a unity-gain bandwidth (UGBW) particularly for use in continuous-time delta-sigma modulators (CT ΔΣMs). Unlike well-known existing compensation topologies [1], the proposed compensation technique provides both a maximum UGBW and an adequate phase margin (PM) by appropriate non-dominant pole and zero positions. The proposed topology performance is validated by SPICE simulation using 28nm CMOS device models.

Power-efficient amplifier frequency compensation for continuous-time delta-sigma modulators

A circuit for calibrating selective coefficients of a delta-sigma modulator is provided. The circuit includes a calibration logic module that is coupled to one of a plurality of stages of the delta-sigma modulator. The calibration logic module measures the oscillating frequency of a respective stage and compares it to a reference frequency. The calibration logic adjusts a selective circuit component associated with the respective stage so that the reference frequency and the oscillating frequency match.

Calibration of time constants in a continuous-time delta-sigma converter

A clock enable system for a multichip device includes a first integrated circuit including a clock signal and at least a second integrated circuit including at least one functional block periodically requiring clock signals from the first integrated circuit; a clock required circuit responsive to each functional block for providing a clock required signal in response to activation of any one or more of the functional blocks; and a clock enable circuit responsive to the clock required signal for enabling the first integrated circuit to provide clock signals to the functional blocks on the second integrated circuit.

Jeffrey C. Gealow

Papers

A 2.8 mW ΔΣ ADC with 83 dB DR and 1.92 MHz BW using FIR outer feedback and TIA-based integrator

Sample rate converter with rational numerator or denominator

Power-efficient amplifier frequency compensation for continuous-time delta-sigma modulators

Calibration of time constants in a continuous-time delta-sigma converter

Clock enable system