J
Jeffrey H. Seltzer
Researcher at Xilinx
Publications - 14
Citations - 359
Jeffrey H. Seltzer is an academic researcher from Xilinx. The author has contributed to research in topics: Programmable logic device & Product term. The author has an hindex of 9, co-authored 14 publications receiving 359 citations.
Papers
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Patent
Macrocell with product-term cascade and improved flip flop utilization
David Chiang,Napoleon W. Lee,Thomas Y. Ho,David A. Harrison,Nicholas Kucharewski,Jeffrey H. Seltzer +5 more
TL;DR: In this article, a programmable logic device having macrocells enables gate cascades between macrocells to occur with a faster signal transit time, while preserving the flip flop function of the cascaded macrocells by reallocating a redirectable flip-flop reset product term (42) to the flipflop input.
Patent
Method and system for HDL global signal simulation and verification
Anthony D. Williams,Jeffrey H. Seltzer,Carol A. Fields,Roberta E. Fulton,Dhimant Patel,Veena N. Kumar +5 more
TL;DR: In this paper, a verification method for HDL designers is disclosed providing access to all the functionality relating to global networks currently available to the schematic designers and allowing reuse of the testbench without losing HDL code portability.
Patent
High speed product term allocation structure supporting logic iteration after committing device pin locations
TL;DR: In this article, a macrocell for flexibly routing product terms from an AND array to output terminals of a programmable logic device is proposed, where the direction in which the product terms are exported can be controlled.
Patent
Structure and method for arithmetic function implementation in an EPLD having high speed product term allocation structure
TL;DR: An EPLD having improved routing and arithmetic function implementation characteristics as discussed by the authors allows for rapid implementation of arithmetic functions without unnecessarily tying up device processing and interconnect resources or unnecessarily delaying processing.
Patent
Circuit for partially reprogramming an operational programmable logic device
Napoleon W. Lee,Derek R. Curd,Jeffrey H. Seltzer,Jeffrey Goldberg,David Chiang,Kameswara K. Rao,Nicholas Kucharewski +6 more
TL;DR: In this article, an instruction blocking circuit selectively blocks programming instructions on the instruction bus from one or more of the function blocks while allowing the other function blocks to receive the programming instructions.