J
Jeffrey P. Tobin
Researcher at Hewlett-Packard
Publications - 8
Citations - 314
Jeffrey P. Tobin is an academic researcher from Hewlett-Packard. The author has contributed to research in topics: Data compression & Content-addressable memory. The author has an hindex of 5, co-authored 8 publications receiving 314 citations.
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Patent
Apparatus and methods for Lempel Ziv data compression with improved management of multiple dictionaries in content addressable memory
TL;DR: In this article, a standby dictionary is used to store a subset of encoded data entries previously stored in a current dictionary, and a selective overwrite dictionary swapping technique was used to allow all data entries to be used at all times for encoding character strings.
Patent
Apparatus and method for managing multiple dictionaries in content addressable based data compression
TL;DR: In this paper, a standby dictionary is used to store a subset of encoded data entries previously stored in a current dictionary to reduce the loss in data compression caused by dictionary resets, and data is compressed/decompressed according to the address location of data entries contained within a dictionary built in a content addressable memory (CAM).
Patent
Memory circuit for lossless data compression/decompression dictionary storage
TL;DR: In this paper, the address location of data entries contained within a dictionary built in a content addressable memory is encoded as new data entries within the dictionary and stored in a new address location for later use.
Patent
Apparatus and method for lempel ziv data compression with management of multiple dictionaries in content addressable memory
TL;DR: In this article, a standby dictionary is used to store a subset of encoded data entries previously stored in a current dictionary to reduce the loss in data compression caused by dictionary resets, and a selective overwrite dictionary swapping technique was used to allow all data entries to be used at all times for encoding character strings.
Patent
Data compression dictionary access minimization
TL;DR: A logic circuit in an integrated circuit implementation of an adaptive data compression algorithm which uses a RAM to store dictionary entries is described in this article, where the logic circuit generates predetermined codewords for single-character strings without accessing the dictionary.