This paper proposes a novel algorithm and its very large scale integration design for context-based adaptive variable length code (CAVLC) decoding. In order to improve through put of CAVLC decoder, we propose two new methods, which are multiple level decoding (MLD) and nonzero skipping for run_before decoding (NZS). By performing parallel operations on the level decoder, MLD can decode two levels in one cycle at most situations, and NZS can produce several values of run_ before in the same cycle. These two methods have the advantages of low complexity and regularity. The proposed architecture needs 141 cycles/macroblock. Moreover, the proposed CAVLC decoder can run at 33.5 MHz to meet the real time requirement for 1920 × 1088 resolution. The power consumption for the 1920 × 1088 resolution is about 1.83 mW. The operation frequency can be reduced about 29.1% to 71.5% compared with other architectures. With an aid on a lower operation frequency, it is suitable for many low power applications. The synthesis result shows that the gate count is 13175 gates, and the maximum frequency can archive 160 MHz.

A Novel Design of CAVLC Decoder With Low Power and High Throughput Considerations

CABAC is high-compression-ratio entropy coding in HEVC, but it is difficult to be parallelized for speedup. In this paper, a pipelined HEVC CABAC architecture is proposed to increase operating frequency. The proposed CABAC encoder was implemented in 0.18um technology with 158 MHz operating frequency and 45,088 gate counts.

Hardware implementation of HEVC CABAC encoder

Diverse approaches to parallel implementation of H.264 have been proposed; however, they all share a common problem. The entropy decoder in H.264 remains mapped on a single processing element (PE). Due to the inherently sequential and context-adaptive nature of the entropy decoder, it cannot be parallelized. This renders a bottleneck to the performance of the entire decoding process. Depending on the type of the processing core and the video bit-rate, the performance of the entire decoding process is subject to the process of entropy decoding. It is, therefore, needful to research and implement new algorithmic solutions to compensate for this bottleneck, and thereby make optimal use of parallel implementation of H.264 decoder on mainstream multi-core systems. This paper presents a new CAVLC decoding method which is de-rived by constructing custom CAVLC decoding tables using ‘table grouping’. Compared to the conventional [5] ‘sequential table look-up’ method, which requires multiple memory accesses. Our proposed method accesses the custom tables only once for the decoding of any symbol. Moreover, in our proposed method, the symbol decoding time does not depend on the symbol length and it is constant for each symbol, resulting in a nearly linear increase in computational complexity with increase in video fidelity as compared to an non linear increase in earlier proposed methods. Experimental results show that our proposed algorithm features up to 7× higher performance and 83% less memory accesses compared to conventional methods. We compare to three commonly used, state-of-the-art CAVLC algorithms, such as table look-up by sequential search [5], table look-up by binary search [9], and “Moon's method” [16].

Efficient constant-time entropy decoding for H.264

The increasing amount of digital video with supreme quality requires more efficient compression. As the complexity of video coding algorithm is rising, there are more demands for hardware accelerators and customized hardware. Context-based Adaptive Binary Arithmetic Coding (CABAC) is the only entropy coding method adopted in the latest video compression standard, High Efficiency Video Coding (HEVC). Binary Arithmetic Encoder (BAE) is an essential component in CABAC, where the compression process happens. Because of the high data dependency and sequential coding characteristic, it is challenging to parallelize BAE. In this work, we proposed a low-cost and high-throughput hardware architecture for one core of BAE in HEVC. Our 4-stage pipelined BAE architecture is capable of processing one regular bin and up to 4 bypass bins per clock cycle with 30% reduction in terms of area when compared with the designs for one-core CABAC architecture. The design can compress an average of 1.4 bins per cycle. It achieves a throughput of 1 Gbin/s at the maximum operating frequency of 810 MHz with the area of 2.2 kGEs and the power consumption of 2.0 mW in Nangate 45nm technology.

Efficient Binary Arithmetic Encoder for HEVC with multiple bypass bin processing

Hardware Implementation of HEVC CABAC Context Modeler

This paper proposes hardware architecture of HEVC (high efficiency video coding) CABAC (context-based adaptive binary arithmetic coding) binarizer. The proposed binarizer was designed and implemented as an independent module that can be integrated into HEVC CABAC encoder. It generates each bin string of each syntax element in a single cycle. It consists of controller module, TU (truncated unary binarization) module, TR (truncated Rice binarization) module, FL (fixed length binarization) module, EGK (k-th order exp-Golomb coding) module, CALR (coeff_abs_level_remaining) module, QP Delta (cu_qp_delta_abs) module, Intra Pred (intra_chroma_pred_mode) module, Inter Pred (inter_pred_idc) module, and Part Mode (part_mode) module. The proposed binarizer was designed in Verilog HDL, and it was implemented in 45 nm technology. Its operating speed, gate count, and power consumption are 200 MHz, 1,678 gates, and 50 uW, respectively.

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Hardware Implementation of HEVC CABAC Binarizer

This paper proposes an H.264/AVC entropy decoder without embedded processor or internal ROM/RAM memories. Conventional H.264/AVC entropy decoders have large internal ROM/RAM memories in context-adaptive variable length decoder. This requires special ROM/RAM fabrication process, which is difficult to be implemented in general digital logic fabrication process. Furthermore, they require embedded processors for bitstream manipulation, which increases area and power consumption. This paper proposes hardwired H.264/AVC entropy decoder without embedded processor, which improves data processing speed and reduces power consumption. Furthermore, it exploits optimized lookup tables and internal buffers without internal ROM/RAM, which reduces hardware size and can be implemented in general digital logic fabrication process. Designed entropy decoder was embedded in H.264/AVC video decoder, and it was verified to operate correctly in the system. It supports QCIF, CIF, QVGA, and VGA format, and its maximum operation frequency is 125 MHz.

Design of H.264/AVC entropy decoder without internal ROM/RAM memories

In this paper, hardware architecture of BAE (binary arithmetic encoder) was proposed for HEVC (high efficiency video coding) CABAC (context-based adaptive binary arithmetic coding) encoder. It can encode each bin in a single cycle. It consists of controller, regular encoding engine, bypass encoding engine, and termination engine. The proposed BAE was designed in Verilog HDL, and it was implemented in 180 nm technology. Its operating speed, gate count, and power consumption are 180 MHz, 3,690 gates, and 2.88 mW, respectively.

Jeonhak Moon

Papers

Hardware implementation of HEVC CABAC encoder

Hardware Implementation of HEVC CABAC Binarizer

Design of H.264/AVC entropy decoder without internal ROM/RAM memories

Hardware Implementation of HEVC CABAC Context Modeler

Hardware Implementation of HEVC CABAC Binary Arithmetic Encoder