A number of intelligent bus interface units (100) are provided in a matrix of orthogonal lines interconnecting processor modules (110) and memory control unit (MCU) modules (112). The matrix is composed of processor buses (105) and corresponding control lines; and memory buses (107) with corresponding control lines (108). At the intersection of these lines is a bus interface unit node (100). The bus interface units function to pass memory requests from a processor module to a memory module attached to an MCU node and to pass any data associated with the requests. The memory bus is a packet-oriented bus. Accesses are handled by means of a series of messages transmitted by message generator (417) in accordance with a specific control protocol. Packets comprising one or more bus transmission slots are issued sequentially and contiguously. Each slot in a packet includes an opcode, address, data, control, and parity-check bits. Write-request packets and read-request packets are issued to the memory-control unit. The memory-control unit responds with reply packets. A message controller (416), bus monitor (413), and pipeline and reply monitor ( 414), run the memory bus in a three-level pipeline mode. There may be three outstanding requests in the bus pipeline. Any further requests must wait for a reply message to free-up a slot in the pipeline before proceeding. Request messages increase the length of the pipeline and reply messages decrease the length of a pipeline. A control message, called a blurb, does not affect the pipeline length and can be issued when the pipeline is not full. The different messages are distinguished by three control signals (405) that parallel the data portion of the bus. The message generator (417) and interface logic (404) drive these control lines to indicate the message type, the start and end of the message, and possible error conditions. The pipeline and reply monitor (414) and the message controller (416) cooperate to insert a reply to a particular request in the pipeline position corresponding to the particular request that invoked the reply.

Interface for use between a memory and components of a module switching apparatus

An arbitration network for use in a data multiprocessing system that includes a functional unit, such as a memory module, that is shared by several requestor devices, such as data processors, wherein access is granted to the shared functional unit through a common data bus on a rotating priority basis and wherein the arbitration cycle of the functional unit for determining priorities of the requestor devices is performed near the end of each operational cycle of the functional unit so that the next requestor device initiates its operational cycle immediately succeeding a current operational cycle then transacting thereby to minimize idle bus periods which would otherwise occur during arbitration cycle sequencing. When the bus is idle and only one request for access is made, the arbitration network foregoes the complete arbitration cycle and issues the grant to the requesting device thereby providing an earlier initiation of the data transfer cycle of the functional unit.

Arbitration scheme for a multiported shared functional device for use in multiprocessing systems

A bus device is provided for use in a data processing system which includes a plurality of bus devices interconnected by a synchronous bus. The bus includes multiplexed data/address/arbitration lines which carry data, address, and arbitration information during respective data, command/address, and arbitration cycles. The bus also includes a BUSY line and a NO ARB line for controlling access to the data/address/arbitration lines. Where constructed as a memory device, the bus device includes memory circuits having a plurality of storage locations, and an interconnecting circuit which monitors the BUSY and NO ARB lines to identify various types of cycles on the bus, and which controls transmission of signals from the memory device over the bus in accordance with information derived by the monitoring means from the BUSY and NO ARB lines.

Bus device for use in a computer system having a synchronous bus

A modular terminal system (10) employs a CPU module (22) connected via a bus (20) to at least one slave module (24, 26, 28, 32, 36). An error condition is detected if a slave module fails to respond to a command by generating an operation acknowledge signal within a predetermined period of time associated with the time required for the slave module to execute the command. A memory mapping device (74) is utilized to decode CPU address signals and generate related signals on a greater number of output lines coupled to the system bus thereby increasing the number of addressable locations otherwise accessible by the CPU. Improved prioritized bus communication is provided by way of a vectored interrupt scheme (210) in which a priority line (212) is coupled in a daisy chain fashion to other slave modules in the system. In the preferred embodiment the system employs distributed CPU modules (22, 24) employing an interprocessor interrupt technique utilizing a pair of commonly accessible storage devices (300, 302). One of the processors may be used as an emulator and a programmable logic array (406) is advantageously utilized in the emulator processor.

Modular terminal system using a common bus

An arbitration apparatus and technique are disclosed in which the request lines from a plurality of potential requestors serve both as interrupt and DMA bus request signal lines to an arbitration device. The arbitration device selects among contending requestors on a priority basis and generates a grant signal interpreted by the requesting devices either as an interrupt grant or a bus grant depending upon whether or not an interrupt acknowledge signal is received. This effectively multiplexes the grant request lines from a plurality of requestors to greatly reduce interconnection complexity and cost. A single interrupt grant/bus grant multi-wire signal cable connects from the arbitration device to the individual requestors. A grant will appear on a single line thereof connected to an individual requestor that has been granted either an interrupt or access to the bus. Interrupt requests from the requestors are ORed together and simultaneously presented to a central controlling microprocessor. The arbitration device determines which requestor will be granted access and, under control of the central control microprocessor, the arbitrator gates an interrupt grant or a DMA grant signal to the device selected by the arbitration mechanism. The dual usage of the grant and request lines by the arbitration device represents a multiplexing feature to further reduce interconnections.

Multiplexed interrupt/dma request arbitration apparatus and method

A priority network utilizing a common bus coupled to a plurality of priority seeking peripheral devices wherein a processor or any number of processors is connected to the common bus. Each successive peripheral device is connected to the common bus in increasing priority order, such that each device will have a unique priority defined. Each peripheral device is provided with an associated peripheral control unit. Each of the peripheral control units is connected in serial fashion on an enabling line with the output of the higher priority control unit providing an enabling input to the next lowest priority peripheral control unit, such that the highest priority device requesting bus access prevents all lower priority devices from gaining access to the common bus until the higher priority device has completed its data transfer.

Jerry R. Washburn

Papers

Priority network for devices coupled by a common bus