In a stacked capacitor type semiconductor device, first and second insulating layers are formed on a semiconductor substrate. A capacitor lower electrode layer is formed in an opening formed within the second insulating layer, and is electrically connected via a contact hole of the first insulating layer to an impurity doped region of the semiconductor substrate. A capacitor insulating layer is formed on the capacitor lower electrode layer, and a capacitor upper electrode layer is formed on the capacitor insulating layer.

Stacked capacitor type semiconductor memory device with good flatness characteristics

A process for fabricating a DRAM semiconductor memory device having a transfer transistor and a storage capacitor with a tree-shaped electrode. The tree-shaped electrode is electrically coupled to a source/drain region of the transistor. The process includes forming a first insulation layer on the device substrate covering the transfer transistor. A first electrically conductive layer is formed over and penetrating the first insulation layer such that it is electrically coupled to the source/drain region. Cylindrical structures are formed on the first conductive layer, forming a recess between the cylindrical structures. A second insulation layer covering the cylindrical structures and a portion of the exposed first electrically conductive layer is formed, with the second insulation layer covering bottom portion of the recesses incompletely. A second electrically conductive layer covering the second insulation layer and the exposed portion of the first conductive layer is formed. Portions of the first and second conductive layers above the cylindrical structures are removed to section the conductive layers, forming tree-trunk and tree-limb portions of the tree-shaped electrode, respectively. The second insulation layer and the cylindrical structures are removed. A dielectric layer is formed over the sectioned first and second conductive layers. A third electrically conductive layer is formed over the dielectric layer, forming an opposing electrode of the capacitor.

Process for fabricating a storage capacitor for semiconductor memory devices

Fabricating a semiconductor memory device with a capacitor includes forming a first insulating layer on a substrate, covering a transfer transistor, and forming a first conducting layer that penetrates the first insulating layer and is electrically coupled to one of a drain or source region of the transfer transistor. Thereafter, a pillar layer is formed at the periphery of and above the first conducting layer, and a second conducting layer is also formed on sidewalls of the pillar layer. Next, alternately a first and a second film layer are formed at least once over the first conducting layer and the second conducting layer. Then, a second insulating layer is formed above the second film layer. After that, a third conducting layer is formed and then defined such that the first, the second, and the third conducting layers, in combination with the second film layer, form a storage electrode of a charge storage capacitor. After removing the pillar layer, the first film layer and the second insulating layer, a dielectric layer is formed on the exposed surface of the first, the second and the third conducting layers. Finally, a fourth conducting layer is formed over the surface of the dielectric layer resulting in the formation of an opposing electrode of the charge storage capacitor.

Method of fabricating a semiconductor memory cell having a tree-type capacitor

A method of fabricating a semiconductor memory device having a capacitor. First, a first insulating layer is formed on a substrate to cover the transistor. Next, a second insulating layer and a first conductive layer are formed in order. The first conductive layer only covers a portion of the second insulating layer to form a branch-like conductive layer. Then, a third insulating layer is formed. An opening is next formed. A second conductive layer is filled into the opening and therefore electrically connected to the source/drain region of the transistor to form a trunk-like conductive layer. Next, the second and the third insulating layers are removed. After a dielectric film is formed on the exposed surfaces of the first and second conductive layers, a third conductive layer is formed on the dielectric film to form an opposed electrode.

Method for forming a semiconductor memory device with a capacitor

A semiconductor memory device including a plurality of memory cells arranged in a matrix manner, each of the memory cells including a transfer transistor constituted by a gate electrode, a gate insulating film, a source region and a drain region, and a charge storage capacitor constituted by a storage node, a dielectric film and a plate electrode, the storage node of the charge storage capacitor including a cylindrical lower electrode formed above the transfer transistor via an insulating layer formed on the transfer transistor and connected to one of the source region and the drain region of the transfer transistor, and a cover type upper electrode formed on the lower electrode and connected with the lower electrode. By the composite structure of the capacitor storage node including the lower structure having the cylinder shape and the cover type upper structure connected with the lower structure, it is possible to utilize efficiently a three-dimensional space structure and thereby achieve an increase in capacitance.

Method for fabricating a capacitor cell in the semiconductor memory device having a step portion

A high-density semiconductor memory device and its manufacturing method are disclosed. The device has a plurality of memory cells, each consisting of one transistor and one capacitor on a substrate in a matrix form. The capacitor, in contact with the source region of the transistor, consists of a storage electrode having a hollow cylindrical electrode with a wall of predetermined thickness, and a column electrode surrounded by the cylindrical electrode. The capacitor further comprises a plurality of bars, a base plate electrode connecting the cylindrical and column electrodes to each other, a dielectric layer coating the whole surface of the storage electrode, and a plate electrode formed on top of the dielectric layer. According to this invention, a greater capacitance may be obtained while avoiding current leakage and the disparity of cell capacitance problems involved with a conventional stack-type capacitor having a ringed structure.

Ji-hong Ahn

Papers

High density semiconductor memory device (MBC cell)