Most modern microprocessors have a deep cache hierarchy to hide the latency of accessing the main memory. Thus, with the increase in the number of cores, the shared Last-Level Cache (LLC) also increases, which consumes a large portion of the chip's total power and area. The same cache hierarchy can represent an extra latency barrier for applications with poor temporal and spatial locality. Therefore, sophisticated solutions should ensure optimal resource utilization to mitigate cache problems. In this scenario, an adaptive cache mechanism can benefit such applications, improving general system performance and decreasing energy consumption. When multiple programs are running, adapting the use of the LLC for each application avoids cache conflicts and cache pollution, increasing system performance. In this paper, we assess two approaches based on regression and classification models to adapt the use of the LLC during run-time, both using hardware counters. Analyzing the efficiency and overhead of each model through SPEC CPU 2006 and 2017, we observe a better performance for the classification model based on the Random Forest algorithm for both single and multi-program workloads. 

Comparison of Different Adaptable Cache Bypassing Approaches

As the number of cores increases, more cores and threads share the Last-Level Cache (LLC), which consumes a large portion of the chip’s total power and area. Therefore, sophisticated solutions must guarantee the best resource usage addressing cache conflicts and cache pollution problems. This work exploits the knowledge that many applications present poor temporal and spatial locality. Thus, an adaptive cache mechanism can benefit such applications, improving general system performance and decreasing energy consumption. In this paper, we propose an online and application-aware predictor to adapt the use of LLC. As a result, DyCa shows up to 22% and 21% performance increases in single and multi-program workloads, respectively.

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DyCa: Dynamically Adaptable Cache Bypassing Mechanism

Most modern microprocessors have a deep cache hierarchy to hide the latency of accessing the main memory. Thus, with the increase in the number of cores, the shared Last-Level Cache (LLC) also increases, which consumes a large portion of the chip's total power and area. The same cache hierarchy can represent an extra latency barrier for applications with poor temporal and spatial locality. Therefore, sophisticated solutions should ensure optimal resource utilization to mitigate cache problems. In this scenario, an adaptive cache mechanism can benefit such applications, improving general system performance and decreasing energy consumption. When multiple programs are running, adapting the use of the LLC for each application avoids cache conflicts and cache pollution, increasing system performance. In this paper, we assess two approaches based on regression and classification models to adapt the use of the LLC during run-time, both using hardware counters. Analyzing the efficiency and overhead of each model through SPEC CPU 2006 and 2017, we observe a better performance for the classification model based on the Random Forest algorithm for both single and multi-program workloads.

As the number of cores on a processor chip increases, the capacity and the number of levels of the cache hierarchy increases, which causes higher energy consumption of the computing system. However, the usage of a cache hierarchy may vary significantly among applications. Thus, determining an appropriate cache hierarchy for each application is crucial to improve performance and energy efficiency. In this paper, we propose a mechanism to improve energy efficiency by adapting a cache hierarchy to individual applications. First, our mechanism bypasses and disables some of the cache levels if their contributions to performance are small. Then, based on the cache utility, the mechanism optimizes the capacity and associativity of the last-level cache. The experimental results with the PARSEC benchmarks show that the proposed mechanism can improve energy efficiency by 26% and 10%, compared with the baseline and cache-level bypassing mechanisms, respectively.

Jiaheng Liu

Papers

A Conflict-Aware Capacity Control Mechanism for Last-Level Cache