String matching is a problem of finding all occurrences of a short pattern on a relatively long reference string. While a number of methods have been presented, most published implementations assume several restrictions due to some practical issues. We focus on the restriction of the alphabet size, which is usually set to be 256 in many string matching libraries. When strings must be handled over an alphabet with a size greater than the limit provided by the given implementation, each character should be represented as a composite alphabet which involves combinations of two or more characters in the restricted alphabet set. In this case, potential false positives can sometimes occur, which may cause a decline in the performance in output-sensitive string matching systems, such as the FM-index. In this paper, we empirically compare various configurations of composite alphabets using FM-index, and show how they affect the performance in terms of the number of false positives and the searching time.

An Efficient Composite-Alphabet Transform for String Matching under a Restricted Alphabet Set

Many hardware-based regular expression matching architectures are proposed for high performance matching. In particular, regular expression processors such as ReCPU and SMPU perform pattern matching in a similar approach to that used in general purpose processors, which provide the flexibility when updating patterns. However, these processors are inefficient in performing class matching since they do not provide character class matching capabilities. This paper proposes an instruction set and architecture of a regular expression matching processor, which can support character class matching. The proposed processor can efficiently perform character class matching since it includes character class, character range, and negated character class matching capabilities.

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Regular Expression Matching Processor Architecture Supporting Character Class Matching

Regular expression matching is a computational intensive task, used in applications such as intrusion detection and DNA sequence analysis. Many hardware-based regular expression matching architectures are proposed for high performance matching. In particular, regular expression matching processors such as ReCPU have been proposed to solve the problem that full hardware solutions require re-synthesis of hardware whenever the patterns are updated. However, ReCPU has inefficient failure processing due to data backtracking. In this paper, we propose an efficient failure processing architecture for regular expression processor. The proposed architecture uses the failure bit included in instruction format and provides efficient failure processing by removing unnecessary data backtracking.

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Jianping Wang

Papers

A pipelined processor architecture for regular expression string matching