Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an in-depth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing designers at architectural, logical, and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems.

/pdf/power-minimization-in-ic-design-principles-and-applications-4l53tahw7t.pdf

Power minimization in IC design: principles and applications

Minimization of power consumption in portable and battery powered embedded systems has become an important aspect of processor and system design. Opportunities for power optimization and tradeoffs emphasizing low power are available across the entire design hierarchy. A review of low-power techniques applied at many levels of the design hierarchy is presented, and an example of low-power processor architecture is described along with some of the design decisions made in implementation of the architecture.

/pdf/low-power-design-for-embedded-processors-4c50cof2pg.pdf

Low-power design for embedded processors

Low power has emerged as a principal theme in today’s electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an in-depth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing designers at architectural, logical, and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems.

https://cs.gmu.edu/~jpsousa/classes/699/papers/pedram_1996.pdf

Tutorial and Survey Paper Power Minimization in IC Design: Principles and Applications

Because of the continuous scaling of feature size and the increasing demand of mobile communication devices, power dissipation has become a major concern of integrated circuit design. Students in electrical and computer engineering will find it very helpful to learn low-power circuit design techniques before they enter the workforce. This work introduces several fundamental low-power design techniques and provides some examples to help students understand design methodologies.

Teaching low-power electronic design in electrical and computer engineering

This paper addresses the optimization of a circuit for low power using transistor reordering. The optimization algorithm relies on a stochastic model of a static CMOS gate that includes the power of internal nodes of the gate. This power-consumption model depends on the switching activity and the equilibrium probabilities of the inputs of the gate. The model allows an exploration of the different configurations of a gate that are obtained by reordering its transistors. Thus, the best configuration of each gate is selected and the overall power consumption of the circuit is reduced.

/pdf/optimizing-cmos-circuits-for-low-power-using-transistor-3wgo2mxhk3.pdf

Optimizing CMOS circuits for low power using transistor reordering

The goal of transistor reordering for a logic gate is to reduce the propagation delay as well as the charging and discharging of internal capacitances to achieve low power consumption. In this paper, based on the input signal probabilities and transition densities, we propose a set of simple transistor reordering rules for both basic and complex CMOS gates to minimize the transition counts at the internal nodes. The most attractive feature of this approach is that not only the power consumption is reduced efficiently, but also the other performances are not degraded. Experimental results show that this technique typically reduces the power by about 10% in average, but in some cases the improvement is even 35%.

/pdf/transistor-reordering-rules-for-power-reduction-in-cmos-1aeu9t3ixu.pdf

Transistor reordering rules for power reduction in CMOS gates

http://ieeexplore.ieee.org/iel2/3478/10306/00486193.pdf

Jiing-Yuan Lin

Papers

Transistor reordering rules for power reduction in CMOS gates

Transistor reordering rules for power reduction in CMOS gates