This review paper presents an overview of readout architectures and analog-to-digital converters (ADCs) for 3D-stacked CMOS image sensors (CIS) with their advantages and challenges. Depending on the application requirements, a suitable 3D-stacked readout architecture will be proposed. While most ADCs to date have been reported in planar CIS, this paper ports these designs to a 3D-stacked CIS and compares the different ADC topologies for this 3D-stacked context in terms of noise, speed and power efficiency. The comparison shows that the ramp and incremental $\Delta \Sigma $ ( $\text{I}\Delta \Sigma $ ) ADCs can achieve a better overall performance compared to the SAR and cyclic ADCs by a factor of ~3 better for 3D-stacked CIS. In addition, ramp and $\text{I}\Delta \Sigma $ ADCs can both achieve (very) low fixed-pattern noise values.

Analysis and Comparison of Readout Architectures and Analog-to-Digital Converters for 3D-Stacked CMOS Image Sensors

In this paper, a 10
-
bit
d
igital
Correlated Double
Sampling (
CDS
)
high
-
speed CMOS Image Sensor
designed
in 65nm BSI technology
for a 1.1μm pixel
is proposed.
The
readout
architecture has been developed to read a 13Mpix
sensor (4248 x 3216) at 55frames/s
,
requiring
a row time of
5.5μ
s
.
The
readout is based on a Piece
-
Wise Linear (PWL)
ramp generator
implementing a
n
I/C structure
.
T
wo
innovative
calibration
technique
s
for output data
linearization are investigated

Piece-wise-linear ramp ADC for CMOS imager sensor and calibration techniques

A series of novolac phenolic polymeric networks (NPPN) were prepared via an acid-catalyzed polycondensation reaction of formaldehyde with chalcones possessing a p-phenolic OH group. When p-hydroxybenzaldehyde was treated with formaldehyde under the same conditions, a phenolic polymer (PP) was obtained. The resulting polymers were isolated in excellent yields (83–98%). Isolated polymers (NPPN, PP) were characterized using FTIR, TGA, and XRD. The results obtained from the TGA revealed that all prepared phenolic polymers have high thermal stability at high temperatures and can act as thermosetting materials. XRD data analysis showed a high degree of amorphousness for all polymers (78.8–89.2%). The electrical conductivities and resistivities of all chalcone-based phenolic networks (NPPN) and p-hydroxybenzaldehyde polymer (PP) were also determined. The physical characteristics obtained from the I-V curve showed that the conductivity of phenolic polymers has a wide range from ultimately negligible values of 0.09 µS/cm up to 2.97 μS/cm. The degree of polarization of the conjugated system’s carbonyl group was attributed to high, low, or even no conductivity for all phenolic polymers since the electronic effects (inductive and mesomeric) could impact the polarization of the carbonyl group and, consequently, change the degree of the charge separation to show varied conductivity values.

/pdf/novel-novolac-phenolic-polymeric-network-of-chalcones-2189dv29.pdf

Novel Novolac Phenolic Polymeric Network of Chalcones: Synthesis, Characterization, and Thermal–Electrical Conductivity Investigation

Computing in Memory (CIM) is reported as one of the most promising non-Von-Neumann computing architectures to replace the existing digital AI processor architecture. Compared with digital-based computation, CIM shows advantages in computing density, energy efficiency, and throughput. However, it requires a large analog-to-digital array to quantize the column-parallel analog Multiply-Accumulate (MAC) results with tight area, high speed, and low power requirements. In this paper, we first discuss the design trade-off between different ADC architectures for CIM accelerators. To improve the overall system efficiency, a 3-8bit reconfigurable hybrid ADC architecture with successive-approximation and single-slope stages is proposed, particularly emphasizing the reconfigurability of the conversion speed and bit-resolution for different computation mode. A prototype is designed and simulated in 65-nm CMOS, which occupies an area of l90$\mu$m $\times$ 5$\mu$m and consumes a power of 48$\mu$W at 8-bit conversion mode, achieving 7.87-bit ENOB and 10.2 fJ/conv.

A 3-8bit Reconfigurable Hybrid ADC Architecture with Successive-approximation and Single-slope Stages for Computing in Memory

This paper proposes a 13-bit fully parallel two-step single slope (TS-SS)ADC for high speed CMOS image sensors. The ADC design method is based on the idea of time sharing and time compression, advances the fine conversion time to the coarse conversion time period, and solves the time redundancy problem of the traditional method. Based on the 55nm1P4M CMOS process, the differential nonlinearity (DNL) and the integral nonlinearity (INL) are simulated to be =0.8/−0.8 LSB and +2.1/−3.5LSB, respectively. The Conversion time of the 13-bit ADC is 512 ns. The effective number of bits (ENOB) is 11.33 bits and the power consumption is $47 \mu$ W.

A 13-Bit High Speed Two-Step Single Slope ADC Design Method for Hundreds of Mpxiel CMOS Image Sensors

A low-power column-parallel gain-adaptive single-slope analog-to-digital converter (ADC) for CMOS image sensors is proposed. The gain-adaptive function is realized with the proposed switched-capacitor based gain control structure in which only minor changes from the traditional single-slope ADC are required. A switched-capacitor controlled dynamic bias comparator and a flip-reduced up/down double-data-rate (DDR) counter are proposed to reduce the power consumption of the column circuits. A 12-bit current steering digital-to-analog converter (DAC) with a two-dimensional gradient error tolerant switching scheme is adopted in the ramp generator to improve the linearity of the ADC. The proposed techniques were experimentally verified in a prototype chip fabricated in the TSMC 180 nm CMOS process. A single-column ADC consumes a total power of 63.2 μ W and occupies an area of 4.48 μ m × 310 μ m. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) of the ADC are −0.43/+0.46 least significant bit (LSB) and −0.84/+1.95 LSB. A 13-bit linear output is acquired in nonlinearity within 0.08% of the full scale after calibration.

https://www.mdpi.com/2079-9292/9/5/757/pdf

A Low-Power Column-Parallel Gain-Adaptive Single-Slope ADC for CMOS Image Sensors

A low power column parallel single-slope ADC with power supply noise suppression for CMOS image sensors is proposed. The ADC is composed of a dynamic bias comparator and a novel up/down double-data-rate (DDR) counter in the column. The column ADCs are divided into groups and several control signals are delayed by groups to avoid transient large current from source. A 12-bit current steering DAC with 2-dimension gradient error tolerant switching scheme is adopted as the ramp generator to improve the linearity of the ADC. The proposed techniques are experimentally verified in a prototype chip fabricated in the TSMC 180nm CMOS process. A single-column ADC consumes a total power of 63.2μW and occupies an area of 4.48μm × 310μm. The measured DNL and INL of the ADC are −0.43/+0.46 LSB and −0.84/1.95 LSB.

A 63.2μW 11-Bit Column Parallel Single-Slope ADC with Power Supply Noise Suppression for CMOS Image Sensors

The discrete-time amplifier has the property of sample and hold, thus it is difficult to adopt local feedback method to deal with offset and flicker noise. A calibration-free swap-combine noise cancellation technique is proposed to remove the input-pair-introduced mismatch in discrete-time amplifiers with keeping the same external interface so it can directly replace the original amplifier. The proposed method can eliminate the flicker noise by modifying the noise transfer function, as well as achieve significant offset suppression. Simulation of a prototype shows that it can reduce the offset root mean square from 10mV to 0.25mV. Benefiting from avoiding calibration loops, the proposed method can also deal with input common-mode voltage variation and temperature drift, as well as reducing the calibration area cost and initial delay.

A Swap-Combine Offset & Flicker Noise Cancellation Technique for Discrete Time Amplifier

A novel high dynamic range high speed column parallel single-slope ADC for CMOS image sensors is proposed. A gain adaptive structure is realized employing column lateral capacitors. With the help of a configurable up/down counter, this structure is compatible with dual correlated double sampling (CDS) scheme which acquires a capability of high noise suppression with no additional memories used. The nonlinearity of the proposed ADC is within 0.73% without extra calibration. Compared with conventional single-slope ADCs, the gain adaptive ADC extends dynamic range by 12dB in the same conversion time.

Jingwei Wei

Papers

A Low-Power Column-Parallel Gain-Adaptive Single-Slope ADC for CMOS Image Sensors

A 63.2μW 11-Bit Column Parallel Single-Slope ADC with Power Supply Noise Suppression for CMOS Image Sensors

A Swap-Combine Offset & Flicker Noise Cancellation Technique for Discrete Time Amplifier

A Gain-Adaptive Single-Slope ADC Employing Column Lateral Capacitors for CMOS Image Sensors