A digital storage element (e.g., a flip-flop or a latch) comprise a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to said master transparent latch. The slave transparent latch comprises dedicated functional data and scan data output ports. The digital storage element operates in a functional mode or in a scan mode. While in the scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch. The first and second clock signals are non-overlapping and, as such, avoid the digital storage element from creating hold violations.

Digital storage element architecture comprising dual scan clocks and gated scan output

A logic device includes a data input, a scan test input, a clock demultiplexer, and a master latch. The clock demultiplexer is responsive to a clock input to selectively provide a first clock output and a second clock output. The master latch is coupled to the data input and to the scan test input and includes an output. The master latch is responsive to the first clock output of the clock demultiplexer and the second clock output of the clock demultiplexer to selectively couple the data input or the scan test input to the output.

Logic device and method supporting scan test

A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port. The data input ports are coupled to a two-input, one-output multiplexer adapted to receive the functional data signals and to selectively output one of the functional data signals. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports. While operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping.

Digital storage element architecture comprising integrated 2-to-1 multiplexer functionality

A system and method for testing an integrated circuit is provided. The illustrative embodiment provides a scan cell for use with automatic test pattern generation (ATPG). In the scan cell of the illustrative embodiment, a flip-flop is configured as a master storage element and a latch is configured as a slave storage element. During standard operating mode, the flip-flop and the latch operate as standard storage elements in the circuit. During a test mode, the flip-flop and the latch form a shift register for shifting test pattern data through the circuit to identify and detect any faults in the circuit design.

Modeling custom scan flops in level sensitive scan design

A series of secondary or “shadow” storage elements are employed that duplicate, or “shadow”, the information in a circuit's core logic shadowed functional registers. These shadow storage elements are then coupled to form a separate, independently-addressable shadow scan path. The information contained in the shadowed functional registers of a circuit is then shifted out via the shadow scan path without altering the shadowed functional registers using special commands issued from a JTAG controller.

Method and apparatus for testing and debugging a circuit

A circuit, an integrated flip flop, to receive an input in response to a clock signal. The integrated flip flop has a first and second slave latch and a master latch. The first slave latch receives an output from the master latch in response to the clock signal and a control signal for a first test mode of operation. The second slave latch receives an output from the master latch in response to the clock signal in one of a second test mode of operation or a normal functional mode of operation.

Joachim Priesnitz

Papers

Method and apparatus for integrated flip-flop to support two test modes