Convolutional coding is a coding scheme often employed in deep space communications and more recently in digital wireless communications Viterbi decoders are used to decode convolutional codes Viterbi decoders employed in digital wireless communications are complex and dissipate large power With the proliferation of battery powered devices such as cellular phones and laptop computers, power dissipation, along with speed and area, is a major concern in VLSI design In this project, a novel architecture, low-complexity design of Viterbi decoders for wireless applications is proposed The focus of my design is the modified trace back approach for final decoding A 4 state Viterbi decoder following the proposed architecture is implemented and the synthesis results are presented Testing is done by simulating the synthesized model on MODEL SIM

FPGA Implementation of a Low Complexity Efficient Traceback Viterbi Decoder for Wireless Applications

Viterbi is an algorithm for error correction in the transmission of messages. It requires coding and decoding stages in the sender and receiver, respectively. These type of algorithms are very useful for the transmission of a type of messages where some degree of error in the received message is acceptable, such as, voice and video. The coding allows some error detection and correction. In this paper we present an architecture for the Viterbi Decoder. Using this initial structure, we have applied a set of transformation techniques aiming for a power optimized implementation. These techniques include pipelining, operation reduction/substitution and the reduction of transition activity. We show that it is possible to reduce the circuit's power consumption by more than half without impacting excessively on the area.

João Portela

Papers

Power Optimized Viterbi Decoder Implementation through Architectural Transforms