International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

In this paper we present a design-for-debug (DFD) reconfigurable infrastructure for SoCs to support at-speed in-system functional debug. A distributed reconfigurable fabric inserted at RTL provides a debug platform that can be configured and operated post-silicon via the JTAG port. The platform can be repeatedly reused to configure many debug structures such as assertions checkers, transaction identifiers, triggers, and event counters.

A reconfigurable design-for-debug infrastructure for SoCs

This paper presents a compression/decompression scheme based on selective Huffman coding for reducing the amount of test data that must be stored on a tester and transferred to each core in a system-on-a-chip (SOC) during manufacturing test. The test data bandwidth between the tester and the SOC is a bottleneck that can result in long test times when testing complex SOCs that contain many cores. In the proposed scheme, the test vectors for the SOC are stored in compressed form in the tester memory and transferred to the chip where they are decompressed and applied to the cores. A small amount of on-chip circuitry is used to decompress the test vectors. Given the set of test vectors for a core, a modified Huffman code is carefully selected so that it satisfies certain properties. These properties guarantee that the codewords can be decoded by a simple pipelined decoder (placed at the serial input of the core's scan chain) that requires very small area. Results indicate that the proposed scheme can provide test data compression nearly equal to that of an optimum Huffman code with much less area overhead for the decoder.

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An efficient test vector compression scheme using selective Huffman coding

We present a technique for compacting test response data using combinational logic circuits. Our compaction technique enables up to an exponential reduction in the number of pins required to collect test response from a chip. The combinational circuits require negligible area, do not add any extra delay during normal operation, guarantee detection of defective chips even in the presence of sources of unknown logic values (often referred to as Xs) and preserve diagnosis capabilities for all practical scenarios. The technique has minimum impact on current design and test flows, and can be used to reduce test time, test data volume, test-I/O pins and tester channels, and also to improve test quality.

X-compact: an efficient response compaction technique for test cost reduction

X-Compact is an X-tolerant test response compaction technique. It enables up to exponential reduction in the test response data volume and the number of pins required to collect test response from a chip. The compaction hardware requires negligible area, does not add any extra delay during normal operation, guarantees detection of defective chips even in the presence of unknown logic values (often referred to as X's), and preserves diagnosis capabilities for most practical scenarios. The technique has minimum impact on current design and test flows, and can be used to reduce test time, test-data volume, test-input/output pins and tester channels, and also to improve test quality.

X-compact: an efficient response compaction technique

Test approaches that can be combined with multisite, like reduced pin-count test, low channel cost ATE, and bandwidth matching, are becoming pervasive. Yet their economic benefits, the tradeoffs, and the long-term scalability of their benefits during technology progress, are not well understood In this paper the benefits and tradeoffs will be analyzed using technical cost modeling. The dependency of the benefits on the application are analyzed by modeling the test cost for 4 different applications. It is shown that the mentioned test approaches can result in a significant and scalable reduction of the Cost of Test.

Test economics for multi-site test with modern cost reduction techniques

This paper presents a new test vector compression technique, which utilizes synergies between Automatic Test Pattern Generation (ATPG) tools provided by EDA (Electronic Design Automation) vendors and Automatic Test Equipment (ATE). The basic approach is to achieve significant compression by agreeing between ATE and ATPG on how to fill don't care values in the test vectors such that these bits need not be stored on ATE and also possibly not communicated to DUT if decompression is done on chip. Our new technique allows sub-vector level fine grained mixing of pseudo-randomly generated bits and ATPG generated bits. Experimental results, on an actual industrial network processor design, show a compression ratio of about 17x.

Test vector compression using EDA-ATE synergies

This paper presents a general economic modeling methodology for digital semiconductor production test approaches. The methodology can be used to quantify trade-offs and evaluate test approaches, including distributed test across test insertions, multi-site test, on-chip/off-chip test trade-offs and ATE architectural tradeoffs, with modeled cost contributions that include test time, die area, yield, time-to-market, and engineering effort. It allows one to forecast how those test approaches scale with technology progress. The economic models are modular and expandable. The modeling methodology will be illustrated on various test approaches.

Tackling test trade-offs from design, manufacturing to market using economic modeling

Typically the DFT features are decided during the design and remain fixed after the design is completed. This makes a device testable only on ATEs, which can satisfy the test requirements for that chip. If such an ATE is not available then the IC either cannot be fully tested, or ATE resources are wasted when it is designed for less capabilities. This paper presents a methodology that builds on the tester retargetable pattern technology for testing ICs on testers with different pin capabilities. Such a capability would be an essential element in reduced pin-count (multi-site) testing. The interfacing needs between the Test Automation World and the Tester Environment are also developed in this paper.

A new methodology for improved tester utilization

The present invention relates to a method for providing an improved generated arbitrary waveform using a sigma-delta modulator with pulse width modulation, said method comprising the steps of sigma-delta modulation of said generated arbitrary waveform, and pulse width modulation of the output signal of said sigma-delta modulator, introducing a minimum pulse width (pwmin) during said pulse width modulation.

Jochen Rivoir

Papers

Test economics for multi-site test with modern cost reduction techniques

Test vector compression using EDA-ATE synergies

Tackling test trade-offs from design, manufacturing to market using economic modeling

A new methodology for improved tester utilization

Sigma-delta modulator with PWM output