1. Introduction. What Is VHDL? History. Capabilities. Hardware Abstraction. 2. A Tutorial. Basic Terminology. Entity Declaration. Architecture Body. Configuration Declaration. Package Declaration. Package Body. Model Analysis. Simulation. 3. Basic Language Elements. Identifiers. Data Objects. Data Types. Operators. 4. Behavioral Modeling. Entity Declaration. Architecture Body. Process Statement. Variable Assignment Statement. Signal Assignment Statement. Wait Statement. If Statement. Case Statement. Null Statement. Loop Statement. Exit Statement. Next Statement. Assertion Statement. Report Statement. More on Signal Assignment Statement. Other Sequential Statements. Multiple Processes. Postponed Processes. 5. Dataflow Modeling. Concurrent Signal Assignment Statement. Concurrent versus Sequential Signal Assignment. Delta Delay Revisited. Multiple Drivers. Conditional Signal Assignment Statement. Selected Signal Assignment Statement. The UNAFFECTED Value. Block Statement. Concurrent Assertion Statement. Value of a Signal. 6. Structural Modeling. An Example. Component Declaration. Component Instantiation. Other Examples. Resolving Signal Values. 7. Generics and Configurations. Generics. Why Configurations? Configuration Specification. Configuration Declaration. Default Rules. Conversion Functions. Direct Instantiation. Incremental Binding. 8. Subprograms and Overloading. Subprograms. Subprogram Overloading. Operator Overloading. Signatures. Default Values for Parameters. 9. Packages and Libraries. Package Declaration. Package Body. Design File. Design Libraries. Order of Analysis. Implicit Visibility. Explicit Visibility. 10. Advanced Features. Entity Statements. Generate Statements. Aliases. Qualified Expressions. Type Conversions. Guarded Signals. Attributes. Aggregate Targets. More on Block Statements. Shared Variables. Groups. More on Ports. 11. Model Simulation. Simulation. Writing a Test Bench. Converting Real and Integer to Time. Dumping Results into a Text File. Reading Vectors from a Text File. A Test Bench Example. Initializing a Memory. Variable File Names. 12. Hardware Modeling Examples. Modeling Entity Interfaces. Modeling Simple Elements. Different Styles of Modeling. Modeling Regular Structures. Modeling Delays. Modeling Conditional Operations. Modeling Synchronous Logic. State Machine Modeling. Interacting State Machines. Modeling a Moore FSM. Modeling a Mealy FSM. A Generic Priority Encoder. A Simplified Blackjack Program. A Clock Divider. A Generic Binary Multiplier. A Pulse Counter. A Barrel Shifter. Hierarchy in Design. Appendix A: Predefined Environment. Reserved Words. Package STANDARD. Package TEXTIO. Appendix B: Syntax Reference. Conventions. The Syntax. Appendix C: A Package Example. The Package ATT_MVL. Appendix D: Summary of Changes. VHDL-93 Features. Portability from VHDL-87. Appendix E: The STD_LOGIC_1164 Package. Package STD_LOGIC_1164. Appendix F: An Utility Package. Package UTILS_PKG. Bibliography. Index.

A VHDL primer

A sampled amplitude read channel is disclosed for disk storage systems which asynchronously samples an analog read signal, adaptively equalizes the resulting discrete time sample values according to a target partial response, extracts synchronous sample values through interpolated timing recovery, and detects digital data from the synchronous sample values using a Viterbi sequence detector. To increase the speed of the read channel, the FIR filters in the equalizer and interpolator are implemented according to a residue number system. Further, the residue number system implementation of the FIR filters uses "one-hot" encoding to decrease power dissipation.

Sampled amplitude read channel employing a residue number system FIR filter in an adaptive equalizer and in interpolated timing recovery

The purpose of this paper is to present the work that has been carried out for the creation of a simulation environment of our network-on-chip (NoC) architecture, called "Proteo" In an intellectual property (IP) based design methodology also the interconnection structures may be treated as IPs The Proteo project is aimed at creating a library of pre-designed communication blocks that can be selected from a component library and configured by automated tools The network implements packet switching in a hierarchical topology We have created a high level model of our network in VHDL, allowing mixed-abstraction level simulation of our synthesizable code for validation

VHDL-based simulation environment for Proteo NoC

A practical RTL level testability analysis methodology is presented in the paper. Both RTL models and functional verification patterns are used in the RTL testability analysis. An RTL fault simulator which is the core of the methodology, is developed to support RTL testability analysis. It is able to generate quantitative RTL fault coverage and provide information for test pattern improvement to improve fault coverage and design modifications to improve testability at the RTL level. Experimental results show that RTL fault coverage is quite close to fault coverage achieved at the gate level when designs are completed and mapped to a technology library. The results also show that effort to improve fault coverage at the RTL level very likely results in corresponding improvement of fault coverage at the gate level. An investigation of some of the causes of difference between RTL fault coverage and actual gate level fault coverage is also reported in the paper.

Improving gate level fault coverage by RTL fault grading

Stratified fault sampling is used in RTL fault simulation to estimate the gate-level fault coverage of given test patterns. RTL fault modeling and fault injection algorithm are developed such that the RTL fault list of a module can be treated as a representative fault sample of the collapsed stuck-at fault set of the module. The RTL coverage for the module is experimentally found to track the gate-level coverage within the statistical error bounds. For a VLSI system, consisting of several modules, the overall coverage is a weighted sum of RTL module coverages. Several techniques are proposed to determine these weights, known as stratum weights. For a system timing controller ASIC, the stratified RTL coverage of verification test-benches was estimated within 0.6% of the actual gate-level coverage. This ASIC consists of 40 modules (9,000 lines of Verilog HDL) that are synthesized into 17,126 equivalent logic gates by a commercial synthesis tool. Similar results on two other VLSI systems are reported.

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Register-transfer level fault modeling and test evaluation techniques for VLSI circuits

Describes how VHDL can be used across the system design process, from specification to the development of maintenance strategies. The contributors provide advanced techniques, and detail how these can be adapted to improve the system development process, reducing time and cost.

Performance and fault modeling with VHDL

Method and apparatus for directly converting the value of an analog signal into a digital format for a prespecified number system. For analog to digital residue number conversion, a plurality of residue channels convert the analog value to a set of digitized residues corresponding to a prespecified set of residue bases.

Joel M. Schoen

Papers

Performance and fault modeling with VHDL

Method and apparatus for direct analog to formatted digital number conversion