An apparatus for interrogating an electronic circuit supported by a substrate includes a tester external to the substrate and comprising an tester transceiver. A testing circuit is supported by the substrate and connected to the electronic circuit. The testing circuit includes a processor and a testing circuit transceiver in communication with the tester transceiver for transmitting instructions from the tester to the processor and for transmitting results of an interrogation from the processor to the tester. The processor being programmed to process instructions from the tester to interrogate the electronic circuit with an interrogation corresponding to the instructions.

Method and apparatus for interrogating electronic equipment components

The present invention provides a method and apparatus for automatically scrubbing ECC errors in memory upon the detection of a correctable error in data read from memory. This is performed by providing in a memory controller (MC) memory control logic for controlling accesses to memory, an ECC error checking and correcting unit for checking data read from memory for errors and correcting any correctable errors found in the read data, a first data buffer for storing the corrected read data output (72, 64) from the ECC error checking and correcting unit and a writeback path having an input end coupled to an output of the first data buffer and an output end coupled to memory. Upon the detection of a correctable error in data read from a particular memory location, the ECC error checking and correcting unit signals to the memory control logic the existence of a correctable error in the read data. The memory control logic then obtains exclusive control over the first data buffer and the writeback path to control writing of the corrected read data onto the writeback path and subsequently to memory.

Method and apparatus for automatically scrubbing ecc errors in memory via hardware

A method and apparatus for interrogating an electronic component (20), includes a body (18 or 102) having an interface (10, 24, 108 or 154) for an interrogating device (48/50 or 106) to use as a conduit in reliably performing multiple discrete interrogations of the electronic component (20) without the interrogating device physically touching the electronic component (20).

Method and apparatus for interrogating an electronic component

A live insertion and removal mechanism assures that a sub-assembly being inserted or removed from a live electronic assembly does not disrupt system power and buses and is protected against the negative effects of current surge. An active current control device and related circuitry, and a connector having a plurality of graduated pin lengths effect a controlled ramp-up and ramp-down of power to the sub-assembly inserted into and removed from the live electronic assembly. Additionally, disconnecting selected output drivers from signal and control paths to avoid damage to the drivers upon insertion or removal of the sub-assembly from the live assembly.

Method and apparatus for live insertion and removal of electronic sub-assemblies

The invention generally relates to a method and apparatus for taking an input signal, replicating it a number of times and modifying each of the replicas before routing them to respective output transducers such that a desired sound field is created. This sound field may comprise a directed beam, focussed beam or a simulated origin. In a first aspect, delays are added to sound channels to remove the effects of different travelling distances. In a second aspect, a delay is added to a video signal to account for the delays added to the sound channels. In a third aspect, different window functions are applied to each channel to give improved flexibility of use. In a fourth aspect, a smaller extent of transducers is used top output high frequencies than are used to output low frequencies. An array having a larger density of transducers near the centre is also provided. In a fifth aspect, a line of elongate transducers is provided to give good directivity in a plane. In a sixth aspect, sound beams are focussed in front or behind surfaces to give different beam widths and simulated origins. In a seventh aspect, a camera is used to indicate where sound is directed.

Method and apparatus to create a sound field

An apparatus for determining system configuration in a computer system using only one 8 bit data port. Permanent connections on each of the microprocessor and memory boards provide respective configuration and/or memory information about each board. The signals are stored in serial out shift registers associated with each board that are daisy chained together. These shift registers serially transmit the configuration information to one 8 bit data port, which then transmits this information to the computer system in 8 bit increments. If a given slot is empty it is automatically bypassed in the shift register daisy chain.

Daisy-chained serial shift register for determining configuration of removable circuit boards in a computer system

An arrangement of direct memory access (DMA), interrupt and timer functions in a multiprocessor computer system to allow symmetrical processing. Several functions which are considered common to all of the CPUs and those which are conveniently accessed through an expansion bus remain in a central system peripheral chip coupled to the expansion bus. These central functions include the primary portions of the DMA controller and arbitration circuitry to control access of the expansion bus. A distributed peripheral, including a programmable interrupt controller, multiprocessor interrupt logic, nonmaskable interrupt logic, local DMA logic and timer functions, is provided locally for each CPU. A bus is provided between the central and distributed peripherals to allow the central peripheral to broadcast information to the CPUs, and to provide local information from the distributed chip to the central peripheral when the local CPU is programming or accessing functions in the central peripheral.

Arrangement of DMA, interrupt and timer functions to implement symmetrical processing in a multiprocessor computer system

A digital system provides a serial bus diagnostic port such as, for example, a universal serial bus (USB) diagnostic port. The USB diagnostic port can include a USB slave device operable to interface to a universal serial bus, a flash memory controller interface coupled to the USB slave device and operable to interface to a flash memory controller, and a test access port controller coupled to the USB slave device and operable to interface to a test access port. The diagnostic port can further include a system interface coupled to the USB slave device and operable to interface to an integrated controller independently of an operating system. Via the diagnostic port, a USB testing tool with testing software can access and debug internal logic of the digital system. As an alternative to a USB diagnostic port, the serial bus diagnostic port can be implemented in a variety of wired or wireless implementations such as, for example, an I.E.E.E. 1394 diagnostic port, an Ethernet diagnostic port, or a wireless Internet diagnostic port. Further, the serial bus diagnostic port can, for example, be used for software development, in-factory testing or in-field diagnostics of the digital system.

Serial bus diagnostic port of a digital system

Example embodiments relate to methods for updating firmware of a hardware component included in a computing device. An example method may store an executable firmware update for the hardware component on a machine-readable storage medium. The method may then initiate a firmware update application by a firmware-to-operating system (OS) interface upon boot-up of the computing device. Finally, the method may trigger update of the firmware of the hardware component by starting execution of the executable firmware update. Related computing devices and machine-readable storage media are also disclosed.

Methods and devices for updating firmware of a component using a firmware update application

A method and apparatus which maintains strict ordering of processor cycles to guarantee that a processor write, such as an EOI instruction, is not executed to the interrupt controller prior to the interrupt request from a requesting device being cleared at the interrupt controller, thus maintaining system integrity. Interrupt controller logic is included on each respective CPU board. The processor can access the interrupt controller over a local bus without having to access the host bus or the expansion bus and thus an interrupt controller access could be completed before a previously generated I/O cycle has completed. Therefore, the apparatus which tracks expansion bus cycles and interrupt controller accesses and maintains strict ordering of these cycles to guarantee that an interrupt request is cleared at the interrupt controller prior to execution of write operation to the interrupt controller.

John A. Landry

Papers

Daisy-chained serial shift register for determining configuration of removable circuit boards in a computer system

Arrangement of DMA, interrupt and timer functions to implement symmetrical processing in a multiprocessor computer system

Serial bus diagnostic port of a digital system

Methods and devices for updating firmware of a component using a firmware update application

Apparatus for strictly ordered input/output operations for interrupt system integrity