The present invention includes a memory subsystem comprising at least two semiconductor devices (15, 16 , 17), including at least one memory device (15, 16 or 17), connected to a bus (18), where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices (15, 16 or 17), where the control information includes device-select information and the bus (18) has substantially fewer bus lines than the number of bits in a single address, and the bus (18) carries device-select information without the need for separated device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus (18) and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices (15, 16, 17). The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an Address Valid bus line carry address, data and control information for memory addresses up to 40 bits wide.

Integrated circuit I/O using a high performance bus interface

A subscriber unit for use in a multiple access spread-spectrum communication system includes a spread spectrum radio interface, responsive to a rate function signal from a base station, and first and second despreaders. The base station assigns the rate function spread-spectrum message channels and the first despreader recovers and modifies an information signal one of the spread spectrum message channels. The information channel mode is then modified for processing by the second despreader, with the second despreader supporting a different information signal rate. The subscriber unit has a capability of communicating with a dynamically changing a transmission rate of an information signal which includes multiple spread spectrum message channels. The system includes a closed loop power control system for maintaining a minimum system transmit power level for a radio carrier station and the subscriber units, and system capacity management for maintaining a maximum number of active subscriber units for improved system performance.

Code division multiple access (CDMA) communication system

A technique for training links in a computing system is disclosed. In one aspect, the technique includes configuring a first receiver in a first port using a first training sequence or a second training sequence; transmitting the second training sequence from the first port indicating the first receiver is configured; and receiving a second training sequence transmitted by a second port at the first port, the second training sequence transmitted by the second port indicating that a second receiver in the second port is configured. In a second aspect, the technique includes locking a communication link; handshaking across the locked link to indicate readiness for data transmission; transmitting information after handshaking across the locked link. And, in a third aspect, the technique includes transmitting a first training sequence from a first port and a second port; and synchronizing the receipt of the first training sequence at the first and second ports; transmitting a second training sequence from the first and second ports upon the synchronized receipt of the first training sequence at the first and second ports; and receiving the second training sequence transmitted by the first and second ports and the second and first ports, respectively, in synchrony.

Method for training a communication link between ports to correct for errors

A programmable interface for a peripheral circuit card is provided. The card is intended for use with a particular computer bus architecture, and the interface can be customized by a user for a particular card design. Instead of designing a custom interface chip, the designer can program one or more programmable logic devices on the interface chip to interface with whatever devices are on the peripheral circuit card.

Programmable interface for computer system peripheral circuit card

A system for rapidly acquiring a spreading code, used in a code division multiple access (CDMA) system, comprises a generator for generating a first long code and a second long code, with each long code having a length of N chips. The first long code is different from the second long code. A transmitter transmits the first long code and the second long code at a first phase angle and at a second phase angle, respectively, on a carrier signal over a communications channel using radio waves. The first long code and the second long code may be transmitted at an in-phase (I) angle and at a quadrature-phase (Q) angle, respectively, on the carrier signal. From the communications channel, an I acquisition circuit and a Q acquisition circuit may acquire, in parallel, the first long code and the second long code from the I angle and the Q angle, respectively, of the carrier signal by searching, in parallel, N/2 chips of the first long code and the second long code.

System for using rapid acquisition spreading codes for spread-spectrum communications

A multiple bus system architecture and improved data transfer methods are disclosed for transferring data between a plurality of data processing resources. The bus structure of the present invention includes both a parallel and serial bus which interconnects data processing units and peripheral devices (collectively referred to as "agents") to permit the exchange of data and messages at high speed using a minimum of "handshake" events prior to the actual data transfer. Both the serial and parallel bus protocals are controlled by message control means coupled to each communicating agent. A local bus is coupled to processing agents within the system such that local memory and secondary processing resources may be accessed without impacting data traffic along the parallel bus. Direct access to resources coupled to the local bus of an agent from other bus agents is also controlled by the message control means.

High speed parallel bus and data transfer method

The bus structure comprises both a parallel bus (35) and a series bus (37), which connect to one another data processing units (25, 26) and peripheral devices (30), jointly referred to as "stations", in order to permit the interchange of data and messages at high speed using a minimum of "handshake" events before the actual data transmission. The serial and parallel bus protocols are controlled by message control devices (44, 50), which are coupled to each participating station. A local bus (56) is coupled to processing stations (25, 26) within the system in such a way that access can be made to local memories (54) and secondary processing resources (57) without adversely affecting the data traffic via the parallel bus (35). A direct access by other bus stations to resources (54) coupled to the local bus (56) of one station is likewise controlled by the message control device (44).

John Beaston

Papers

High speed parallel bus and data transfer method

High-speed parallel-bus structure and method of data transmission