A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration. The new configuration data may include off-chip or on-chip data. The present invention typically allocates at least one slice to user data memory and includes means for disabling access to at least one of the N memory cells.

Method of time multiplexing a programmable logic device

A method of optimizing a time multiplexed programmable logic device (PLD) includes entering a circuit design for the PLD, mapping the design to the physical resources of the PLD (wherein the physical resources include configurable logic elements), determining an appropriate micro cycle for each configurable logic element in the design, placing the resources on the PLD, and connecting the resources Optimizing the design may include reducing the number of look up tables or reducing the logic depth of the look up tables If the configurable logic elements include sequential logic elements, then the optimizing step includes rescheduling the sequential logic elements A method of operating a time multiplexed PLD in a logic engine mode includes programming the PLD to implement a design in stages, wherein each stage is one configuration, sequencing the PLD through all the configurations, and storing the results of the logic performed in one configuration in a plurality of micro registers for use in subsequent configurations In one embodiment, the PLD includes a plurality of combinational elements and sequential logic elements, wherein the values stored by the sequential logic elements are stored in the micro registers

Optimizing and operating a time multiplexed programmable logic device

A computer-implemented method of optimizing a time multiplexed programmable logic device includes identifying a micro cycle, identifying all look-up tables (LUTs) from a list of LUTs of the PLD that may be scheduled in the micro cycle, ordering the LUTs in priority order, selecting the M LUTs with the highest priority (wherein M is the number of real LUTs in the PLD), labeling the M LUTs with the current micro cycle number, removing the M LUTs from the list, identifying the next micro cycle, and if labelled LUTs exist, then repeating all steps, otherwise exiting the computer-implemented method. The step of ordering alternatively includes identifying the LUTs with the earliest latest-possible schedule, identifying the LUTs having input nets in which all LUTs are already scheduled, identifying the LUTs that include a pin on a net that has had at least one of its destination instances scheduled, identifying the LUTs that will complete a net that may be introduced in the micro cycle by the addition of a LUT earlier in a list of the LUTs, or identifying the LUTs that include a pin on a net that may be introduced in the micro cycle by the addition of a LUT earlier in a list of the LUTs. In another embodiment, the method includes the first three steps, then further includes determining whether the number of selected LUTs is equal to M, wherein M is less than or equal to the number of real LUTs in the programmable logic device. The steps of labeling and removing are repeated until the number of selected LUTs is equal to M. Then, the M LUTs with the current micro cycle number are labelled and removed from the list. The next micro cycle is then identified. If labelled LUTs exist, then all steps are repeated.

Computer-implemented method of optimizing a time multiplexed programmable logic device

The preferred embodiments described herein provide a medical diagnostic ultrasound imaging system and method in which a non-real-time operating system is used to transfer image data. In one preferred embodiment, a medical diagnostic ultrasound imaging system includes a central processing unit (“CPU”) located outside of the received signal path to transfer image data. The non-real-time operating system can be used, for example, to transfer image data from a hard disk to system memory for display, to transfer image data from system memory to the hard disk for storage, or to scroll image data to view a loop of image data.

Medical diagnostic ultrasound system and method

A computer-implemented method of optimizing a time multiplexed programmable logic device includes identifying a micro cycle, identifying all look-up tables (LUTs) from a list of LUTs of the PLD that may be scheduled in the micro cycle, ordering the LUTs in priority order, selecting the M LUTs with the highest priority (wherein M is the number of real LUTs in the PLD), labeling the M LUTs with the current micro cycle number, removing the M LUTs from the list, identifying the next micro cycle, and if labelled LUTs exist, then repeating all steps, otherwise exiting the computer-implemented method. The step of ordering alternatively includes identifying the LUTs with the earliest latest-possible schedule, identifying the LUTs having input nets in which all LUTs are already scheduled, identifying the LUTs that include a pin on a net that has had at least one of its destination instances scheduled, identifying the LUTs that will complete a net that may be introduced in the micro cycle by the addition of a LUT earlier in a list of the LUTs, or identifying the LUTs that include a pin on a net that may be introduced in the micro cycle by the addition of a LUT earlier in a list of the LUTs. In another embodiment, the method includes the first three steps, then further includes determining whether the number of selected LUTs is equal to M, wherein M is the number of real LUTs in the programmable logic device. The steps of labeling and removing are repeated until the number of selected LUTs is equal to M. Then, the M LUTs with the current micro cycle number are labelled and removed from the list. The next micro cycle is then identified. If labelled LUTs exist, then all steps are repeated.

Computer-implemented method of optimizing a design in a time multiplexed programmable logic device

A microcoded pulse sequencer for real time control of a nuclear magnetic resonance (NMR) magnetic resonance imaging (MRI) system includes a microcode store which is continually loadable. Microinstructions are loaded into a one portion of the store while the sequencer executes micro-instructions out of another portion of the store. Means are provided to ensure that the sequencer never executes micro-instructions currently being loaded, and also ensures (through timing features) that the sequencer can never, over time, execute micro-instructions more rapidly than new micro-instructions can be loaded (i.e., so that the sequencer never "runs out of" micro-instructions). Since the host processor and the microcode sequencer provide for continual loading of the sequencer store while the sequencer is running, the user/programmer may view the control store as an ideal virtual control store having an unlimited size. Programmers may now write NMR microcode sequences without concern for whether they will "fit" into the physical memory space provided by sequencer store. In addition, reloading of the control store is completely transparent to ongoing NMR pulse sequences in the preferred embodiment and causes no troublesome image-degrading interruption of such sequences.

Continually loadable microcode store for MRI control sequencers

A multi-rate sample MRI (magnetic resonance imaging) digital receiver maintains synchronization of digitally processed signals. This multi-rate sample data system is used to demodulate and filter a digitized MRI RF signal. A phase/timing relationship is established between the signal received and processed by the digital receiver, and the physical nuclear magnetic resonance (NMR) process the body being imaged is undergoing. Once established, the phase/timing relationship is maintained for the duration of the particular NMR experiment being performed. Special logic in the digital system ensures that the data output is synchronized with an external synchronous signal controlling data acquisition within the MRI system. Optimum signal processing is performed to minimize the time between the end of the acquisition control signal and the last output from the digital signal processing system.

Synchronized digital signal processor for MRI reception

A local frequency generator employing a single crystal oscillator, latches and direct digital synthesizer circuits digitally produces all signals needed in the transmitter channel of a MRI system to generate MRI transmitter RF pulses. The local frequency generator is operable in both the single side band and double side band modes and has the capability of switching between the modes. The generator is constructed with a phase resetting capability for providing the plural output frequencies needed for making plural MRI slices.

MRI multi-frequency DSB and SSB RF synthesizer

An analog-to-digital sampling rate substantially higher 
than the Nyquist frequency 2f c usually associated with the cut-­
off frequency f c of a low pass NMR response signal filter (21) is 
employed to reduce NMR image artifact caused by aliasing ef­
fects in the digital signal image reconstruction process. In ef­
fect, the outer limits of the displayed NMR image field-of-view 
(in at least one dimension) are defined by the cut-off frequency 
f c of the low pass filter (21) rather than by the sampling rate 
which is, in the preferred exemplary embodiment approxi­
mately as great as 4f c .

John C. Hoenninger

Papers

Continually loadable microcode store for MRI control sequencers

Synchronized digital signal processor for MRI reception

MRI multi-frequency DSB and SSB RF synthesizer

Apparatus and method for reducing aliasing in sagittal or coronal NMR imaging

Prospects for increasing the accessibility of MRI.