A system and method for maintaining logically consistent backups using minimal data transfer are presented A system comprises a backup system having a backup storage device and one or more primary systems having mass storage devices that are to be backed up on the backup storage device The primary systems identify changes that are going to be made to the mass storage device The combined effected locations in the mass storage device of these identified changes are then captured in a static snapshot when the mass storage device is in a logically consistent state Only those data blocks changed since the last backup are then transferred to backup system The backup system can then store these changes or apply the changes to the backup storage device in order to bring the backup storage device current to a particular point in time

Backup system that takes a snapshot of the locations in a mass storage device that has been identified for updating prior to updating

A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. Some of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective set of master cache tags (Etags), including one Etag for each data block stored by the cache memory. Each data processor includes an interface for sending memory transaction requests to the system controller and for receiving cache transaction requests from the system controller corresponding to memory transaction requests by other ones of the data processors. The system controller includes transaction activation logic for activating each said memory transaction request when it meets predefined activation criteria, and for blocking each said memory transaction request until the predefined activation criteria are met. An active transaction status table stores status data representing memory transaction requests that have been activated, including an address value for each activated transaction. The transaction activation logic includes comparator logic for comparing each memory transaction request with the active transaction status data for all activated memory transaction requests so as to detect whether activation of a particular memory transaction request would violate the predefined activation criteria. With certain exceptions concerning writeback transactions, an incoming transaction for accessing a data block that maps to the same cache line a pending, previously activated transaction, will be blocked until the pending transaction that maps to the same cache line is completed.

Transaction activation processor for controlling memory transaction processing in a packet switched cache coherent multiprocessor system

A caching system for a shared bus multiprocessor which includes several processors each having its own private cache memory. Each private cache is connected to a first bus to which a second, higher level cache memory is also connected. The second, higher level cache in turn is connected either to another bus and higher level cache memory or to main system memory through a global bus. Each higher level cache includes enough memory space so as to enable the higher level cache to have a copy of every memory location in the caches on the level immediately below it. In turn, main memory includes enough space for a copy of each memory location of the highest level of cache memories. The caching can be used with either write-through or write-deferred cache coherency management schemes.

Hierarchical cache memory system and method

A system and method for providing a static snapshot, or image, of data stored on a mass storage system are disclosed. First, a preservation memory is cleared and a virtual device is created. Whenever a write is to be performed on the mass storage system, a check is made of the preservation memory to determine if it contains a block associated with the mass storage write address. If there is not, a copy of the block in the mass storage system at the block write address is placed in the preservation memory. Whenever a read is to be performed on the virtual device, a check is made of the preservation memory to determine if it contains a block associated with the virtual device read address. If there is such a block, that block is returned as the result of the virtual device read. Otherwise, the block at the virtual device block read address is returned as the result.

Method and system for providing a static snapshot of data stored on a mass storage system

A is a duel processor system (100) with duplicated memory (114,124) has two modes (10,11) of operation: a converged mode (10) in which one of the two processors (101,102) is active and executing all system tasks while the other processor is inactive; and a diverged mode (11) in which both processors are active and independently executing different tasks. The system automatically changes modes in response to requests such as manual and program control and certain system fault conditions. In diverged mode, the system may be in either of two states of operation (1 and 2). In one state (1) one processor (101) is designated a primary processor, and in the other state (2) the other processor (102) is designated the primary processor. In the converged mode the system may be in either of four states of operaton (3-6). In two of these states (3,4) one processor is active while the other processor is standing by ready to take up execution of tasks from the point where the one processor stoped execution. In the other two of these states (5,6) one processor is active while the other processor is out of service and cannot take up task execution without being initialized. The system 100 makes transitions between the various states in response to requests. Except for transitions of an active processor to an out-of-service condition, the state transitions are transparent to tasks other than fault recovery programs and, upon a fault condition, the faulted program.

Reconfigurable dual processor system

Apparatus for avoiding ambiguous data in a multi-requestor computing system of the type wherein each of the requestors has its own dedicated cache memory. Each requestor has access to its own dedicated cache memory for purposes of ascertaining whether a particular data word is present in its cache memory and of obtaining that data word directly from its cache memory without the necessity of referencing main memory. Each requestor also has access to all other dedicated cache memories for purposes of invalidating a particular data word contained therein when that same particular data word has been written by that requestor into its own dedicated cache memory. Requestors and addresses in a particular cache memory are time multiplexed in such a way as to allow a particular dedicated cache memory to service invalidate requests from other requestors without sacrificing speed of reference or cycle time of the particular dedicated cache memory from servicing read requests from its own requestor.

Multiplexed directory for dedicated cache memory system

Computer system with a main memory and a plurality of requestors (A, B ), each of which having its own dedicated high speed cache memory The data are being transferred between the main memory and the cache memories Each requestor has access to its own as well to the cache memories of the other requestors Each cache memory comprises a data buffer (104) for storing data and a tag buffer (100) for storing addresses of locations in the data buffer (104) If the same data are held in two or more cache memories, then upon writing into its own dedicated cache memory the requestor is connected to the other cache memories containing the corresponding data for purposes of invalidating these data The data buffer (104) has a substantially longer cycle time of the data buffer and after the tag buffer being addressed by its own dedicated requestor (A) a selector (96) is switched, so that another requestor (B) which has written into data can address the tag buffer (100) and invalidate any corresponding entry which may be present

John Clarence Waite

Papers

Multiplexed directory for dedicated cache memory system

Computing systems having high-speed cache memories