A parallel sampling phase detector with linear output response is disclosed. The parallel sampling phase detector for use in data recovery. The device includes a voltage controlled oscillator (VCO) that generates ten separate phase signals using a five stage ring oscillator. Five linear phase detectors are employed in the device, each operating during one of five "window" intervals. The "window" intervals are non-overlapping, and are generated using preselected ones of the VCO output phases. The linear phase detectors each generate, respectively, a variable pulsewidth pump up signal wherein the pulsewidth of the pump up signal is proportional to a phase difference between the input data signal applied to the phase detector, and the output phase signals of the VCO. Each phase detector also generates a pump down signal that has a fixed pulsewidth. A loop filter determines the difference between the pump up and pump down signals and develops a control signal to vary the output frequency and phase of the VCO in accordance therewith. Each phase detector also operates as a deserializer, capturing, during the interval when the respective "window" signal is active, the data signal from the input data stream. The plurality of sampled data signals are captured by a data register, which then outputs an n-bit (5-bit) parallel format data word. The linear phase detector includes means for generating the pump down signal in response to the generation of the pump up signal.

Phase locked loop (PLL) with linear parallel sampling phase detector

An entire radio transceiver can be completely integrated into one IC chip. In order to integrate the IF filters on the chip, a heterodyne architecture with a low IF is used. A single, directly modulated VCO is used for both up-conversion during transmission, and down-conversion during reception. Bond-wires are used as resonators in the oscillator tank for the VCO. A TDD scheme is used in the air interface to eliminate cross-talk or leakage. A Gaussian-shaped binary FSK modulation scheme is used to provide a number of other implementation advantages.

Radio transceiver on a chip

A radio receiver for FM signals having a demodulation system (9) to produce an approximation to an analogue output by either measuring the time intervals between successive zero crossings in the intermediate frequency (I.F.) or by filtering pulses produced at zero crossings of the I.F.

Direct conversion radio receiver for F.M. signals

The building blocks for a low-power tuning system that reduces the phase noise of integrated VCO's are described. The multimodulus prescaler, the phase frequency detector, and the wide-band charge pump have been integrated in a standard bipolar technology with 9-GHz n-p-n transistors and 200-MHz p-n-p transistors. The maximum input frequency of the multimodulus prescaler is 3.2 GHz, the maximum reference frequency of the phase frequency detector is 380 MHz, and the 3-dB bandwidth of the charge pump is 41 MHz at a reference frequency of 300 MHz. The achieved performance enables the use of fully integrated VCO's with relatively high phase noise for reception of satellite digital signals.

A wide-band tuning system for fully integrated satellite receivers

A phase locked loop (PLL) (40) simultaneously has both relatively-low power consumption and relatively-low jitter on a clock output signal. The PLL (40) includes a phase detector (41) and a phase error accumulator (42) connected to the output of the phase detector (41). The phase error accumulator (42) samples an output of the phase detector (41) at a relatively-high clock rate, but accumulates these samples and provides an output thereof to a loop filter (43) at a relatively-low clock rate. Thus the PLL (40) captures short periods of phase delay to maintain low clock output signal jitter, while at the same time, however, the loop filter (43) need only adjust its output periodically, at the relatively-low rate, thereby saving power. The phase detector (41) detects a metastable condition on a phase detector latch (60) and resolves to an up pulse or a down pulse to further reduce clock output signal jitter.

Low-power, jitter-compensated phase locked loop and method therefor

A digital phase and frequency detector is capable of providing a linearized transfer function. The digital phase and frequency detector includes two latches each receiving an input and each providing an output. The output of the latches is combined by a logic gate to generate a reset signal. The linearization is a result of providing a delay to the reset signal. The reset signal is used to reset the two latches within the phase and frequency comparator. This improved phase and frequency comparator eliminates non-linearities which would otherwise be inherent in its transfer function and thereby degrade performance of phase-locked systems employing the comparator. The phase and frequency detector is easily manufactured as an integrated circuit and does not require any external signals in order to eliminate the non-linear region.

Linearized digital phase and frequency detector

A method of using a sample and hold circuit to obtain a substantially ripple free voltage on the holding capacitor is provided by holding the charge capacitor at a constant voltage during the sampling time and by not routinely charging the charge capacitor to the maximum potential available. This provides a virtually constant voltage from which the holding capacitor can be charged. The level to which the charging capacitor is charged is controlled by an error signal. This error signal is reflected onto the holding capacitor, and is used as an output for the sample and hold circuit.

Method for performing a sample and hold function

A frequency generator in which the PLL frequency synthesizer and the VCO are directly modulated by an input serial data stream for providing an FSK modulated RF output signal useful in narrowband data communication systems. The serial data stream may alternatively modulate either the PLL frequency synthesizer or the VCO alone.

FSK Modulator and method for NRZ data transmission utilizing PLL frequency synthesis

A synthesizer is placed in standby mode when a standby portion of a control register is set. Once standby is activated, any detectors and counters are inhibited. The inputs and outputs are reconfigured so as to minimize current drain and to stabilize the VCO control voltage. Recovery from standby is accomplished in two phases. The first phase is started by the receipt of a terminate standby signal. This enables the inputs and starts the counters. The second phase is activated when a signal is received from a feedback counter indicating it has completed a cycle. This causes the preset data to be loaded into the reference counter. The counters are then synchronized; the detector is initialized; and the detector output is enabled. The device also controls an output lock detector and reference frequency signal during the standby mode. The system is also compatible with variable modulus prescalers.

Standby system for a frequency synthesizer

A circuit for alternately providing a first frequency to a receiver stage (20) and a second frequency to a transmitter stage (25) of a transmitter and receive circuit (11). The circuit comprises an oscillator (38), a first switch (33), a second switch (42), and a control circuit (29). The first switch (33) couples information to the oscillator (38) to be transposed on the second frequency during transmission. The second switch (42) couples the oscillator (38) to either the transmitter stage (25) or the receiver stage (20). Prior to changing oscillator frequency the control circuit (29) disables both outputs of the second switch (42). The control circuit (29) alternately tunes the oscillator (38) to the first frequency and enables the second switch (42) such that the oscillator (38) is coupled to the receiver stage (20) and tunes the oscillator (38) to the second frequency, enables the first switch (33), and enables the second switch (42 ) such that the oscillator (38) is coupled to the transmitter stage (25).

John D. Hatchett

Papers

Linearized digital phase and frequency detector

Method for performing a sample and hold function

FSK Modulator and method for NRZ data transmission utilizing PLL frequency synthesis

Standby system for a frequency synthesizer

Transmitter and receiver circuit and method therefor