A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.

Characterization adn reduction of variation for integrated circuits

Variations are characterized in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topographical variation in the integrated circuit, the variations in feature dimension being caused by the topographical variations. The process includes lithography or etch. Predicted characteristics are verified to conform to the design, the characteristics including feature dimensions or electrical characteristics. A process is selected for use in fabricating the integrated circuit based on the relative predicted variations. Chip-level features of a design of an integrated circuit are verified for manufacture within focus limitations of a lithographic tool. Whether a design of a level of an integrated circuit can be lithographically imaged in accordance with the design is predicted, and if it cannot be, the design or processing parameters are adjusted so that it can be.

Characterization and verification for integrated circuit designs

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.

Dummy fill for integrated circuits

Use of models in integrated circuit fabrication

A pattern-dependent model is used to predict characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process. The process includes (a) a fabrication process that will impart topographical variation to the integrated circuit and (b) a lithography or etch process, the lithography or etch process using a mask produced from the design. The lithography or etch process and the fabrication process interact to cause the predicted characteristics to differ from the design. The mask is adjusted in response to characteristics predicted by the model, to reduce the effect of the interacting of the lithography or etch process and the fabrication process. A location on an integrated circuit is predicted for which a lithography tool would not produce a satisfactory feature dimension without a degree of adjustment of the tool during fabrication to accommodate a focus limitation of the tool, and the design of at least one mask derived from the design is adjusted to enable the lithography tool to produce a satisfactory feature dimension at the locations. A virtual adjustment is effected of a distance of a lithographic tool from a location in a region of a wafer, the virtual adjustment being effected by using a mask having a mask layout that has been generated based on a pattern-dependent model prediction that the location in the region of the wafer would not otherwise have a satisfactory feature dimension due to a focus limitation of the lithographic tool. A pattern-dependent model is used to predict topography variations that will occur in an integrated circuit as a result of processing up to a predetermined lithographic process step, and designs of masks used in the lithographic process step are adjusted to accommodate the topography variations.

Adjustment of masks for integrated circuit fabrication

The invention is a capacitively coupled probe which can be used for non-contact acquisition of both analog and digital signals. The probe includes a shielded probe tip, a probe body which is mechanically coupled to the probe tip, and an amplifier circuit disposed within the probe body. The amplifier circuit receives a capacitively sensed signal from the probe tip and produces an amplified signal in response thereto. The amplifier has a large bandwidth to accommodate high-frequency digital signals. Further, the amplifier has a very low input capacitance and a high input resistance to reduce signal attenuation and loading of the circuit being probed. The amplifier circuit is disposed in the probe body closely adjacent to the probe tip in order to reduce stray and distributed capacitances. A reconstruction circuit reconstructs digital signals from the amplified capacitively sensed signal.

Capacitively-coupled test probe

This paper gives a proposal for an analog testability bus that could be used as the basis for a standard such as IEEE P1149.4. The proposed testability structure is imposed on the I/O pin cells of the analog and mixed technology ICs. It is a superset of the existing IEEE/ANSI 1149.1 testability standard for digital ICs and is intended to cooperate with it. This allows for the testing of interconnect failures such as shorts and opens, the testing of discrete analog components and networks between ICs, and supports the testing of analog functions within the ICs themselves. This paper is a companion to the result of a cooperative effort between AT&T, Ford Motor, Hewlett-Packard, Motorola and the University of Colorado at Colorado Springs. >

Structure and metrology for an analog testability bus

An electromagnetic probe is integrated within an integrated circuit or mounted within an IC package to provide a capability for testing continuity between the integrated circuit and a substrate to which the integrated circuit is mounted. In a first embodiment, capacitive test probes are integrated within the integrated circuit, underneath bonding pads. In a second embodiment, Hall-effect devices are integrated within the integrated circuit underneath bonding pads. In a third embodiment, an inductive loop is integrated within the integrated circuit underneath bonding pads. In a fourth embodiment, an IC package assembly includes an internal capacitive test probe for electrical continuity testing. An internal shield may also be used as a capacitive test probe. In a fifth embodiment, an IC package assembly includes an inductive loop within the package for electrical continuity testing. The integrated or intrapackage test probes provide electromagnetic coupling to bonding pads or to a lead frame and to bonding wires (if present), to detect whether there is electrical continuity between an integrated circuit bonding pad or lead frame and conductors on an external substrate. The integrated or intrapackage test probes enable continuity testing for direct-bonding with no package, or for a package assembly even if the package assembly includes grounded shielding or a grounded heat sink.

Integrated or intrapackage capability for testing electrical continuity between an integrated circuit and other circuitry

The present invention is an improved printed circuit board test system in which test probes are positioned to electronically engage a selected device or printed circuit board section on a printed circuit board for testing the printed circuit board for manufacturing defects. The printed circuit board test system uses a bed-of-nails test fixture to ground and excite predetermined sites on a first side of the printed circuit board and a robot to mechanically position test probe(s) at selected test sites on a second side of the printed circuit board. A controller is used to control the movement of the robotic tester and the selection of spring probes in the bed-of-nails fixture to be exited, grounded or measured.

Electrical assembly testing using robotic positioning of probes

A method and apparatus is disclosed for testing integrated circuit interconnect and measuring the value of passive component interconnecting the IC's. Each IC includes both analog and digital circuitry and is provided with a test access port and boundary scan architecture for selectively connecting components to an analog test bus and for testing for the integrity of interconnections. When connected with the test bus, a constant current is supplied to the component and the resulting voltage developed across the bus is used for identifying the value of the component. In a second embodiment each IC includes a pair of buses which permits measurement of the impedance of the switches connecting the components to the test bus.

John E. Mcdermid

Papers

Capacitively-coupled test probe

Structure and metrology for an analog testability bus

Integrated or intrapackage capability for testing electrical continuity between an integrated circuit and other circuitry

Electrical assembly testing using robotic positioning of probes

Method and apparatus for testing integrated circuits in a mixed-signal environment